serial0.v

8051的Verilog实现

         end 
      
      end  
   end 

   //------------------------------------------------------------------
   always @(s0con or smod or clk_ov2 or clk_ov4 or baud_rate_clk)
   begin : baud_clk_sel
   //------------------------------------------------------------------
   case (s0con[7:6])
   //-----------------------------------
   // Modes 1 or 3
   //-----------------------------------
   2'b01, 2'b11 :
      begin
      b_clk = baud_rate_clk ; 
      end
   
   //-----------------------------------
   // Mode 2
   //-----------------------------------
   2'b10 :
      begin
      if (smod)
         begin
         b_clk = clk_ov2 ; 
         end
      else
         begin
         b_clk = clk_ov4 ; 
         end 
      end
   
   //-----------------------------------
   // Mode 0
   //-----------------------------------
   default :
      begin
      b_clk = 1'b0 ; 
      end
   
   endcase 
   end 
   
   //------------------------------------------------------------------
   assign baud_r_clk =
      (
         (s0con[7:6] == 2'b01 | s0con[7:6] == 2'b11)
         &
         (!(adcon[7]))
      ) ? t1ov_rise :
      (
         (s0con[7:6] == 2'b01 | s0con[7:6] == 2'b11)
         &
         ((adcon[7]))
      ) ? baud_rate_ov :
      clk_ov2 ; 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : baud_div_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      baud_r_count <= 1'b0 ; 
      baud_r2_clk <= 1'b0 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // baud_r_clk overflow count
      //--------------------------------
      begin
      if (baud_r_clk)
         begin
         baud_r_count <= ~(baud_r_count) ; 
         end 
         
      //--------------------------------
      // Overflow divide by 2
      //--------------------------------
      if (baud_r_clk & baud_r_count)
         begin
         baud_r2_clk <= 1'b1 ; 
         end
      else
         begin
         baud_r2_clk <= 1'b0 ; 
         end 
      end  
   end 
   
   //------------------------------------------------------------------
   assign baud_rate_clk =
      (smod) ? baud_r_clk :
      baud_r2_clk ; 
   
   //------------------------------------------------------------------
   assign t_baud_clk =
      (s0con[7:6] == 2'b00) ? clk_ov12 :  // mode=0
      t_baud_ov ;                         // mode=1,2,3
   
   //------------------------------------------------------------------
   assign t_shift_clk =
      (t_start) ? t_baud_clk :
      1'b0 ; 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : transmit_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      t_start <= 1'b0 ; 
      t_baud_count <= 4'b0000 ; 
      t_baud_ov <= 1'b0 ; 
      t_shift_reg <= 11'b11111111111 ; 
      t_shift_count <= 4'b0000 ; 
      txd0 <= 1'b1 ; 
      rxd0o <= 1'b1 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Transmit clk divide by 16
      //--------------------------------
      begin
      if (b_clk)
         begin
         t_baud_count <= t_baud_count + 1'b1 ; 
         end 

      if (b_clk & t_baud_count == 4'b1111)
         begin
         t_baud_ov <= 1'b1 ; 
         end
      else
         begin
         t_baud_ov <= 1'b0 ; 
         end 
         
      //--------------------------------
      // Transmit shift enable
      //--------------------------------
      
      //--------------------------------
      if (t_shift_count == 4'b0000 &
         ~(sfrwe & sfraddr == S0BUF_ID))
         begin
         t_start <= 1'b0 ; 
         end
      else if (sfrwe & sfraddr == S0BUF_ID)
         begin
         t_start <= 1'b1 ; 
         end 
         
      //--------------------------------
      // Transmit registers load
      //--------------------------------
      if (sfrwe & sfraddr == S0BUF_ID)
         begin
         case (s0con[7:6])
         //-----------------------------
         // Mode 0
         //-----------------------------
         2'b00 :
            begin
            if (clk_count == 4'b1010 | clk_count == 4'b1011)
              begin
              t_shift_reg[7:0] <= sfrdatai;
              t_shift_reg[8]   <= 1'b1;
              t_shift_count    <= 4'b1001; 
              end
            else
              begin
              t_shift_reg[8:1] <= sfrdatai;
              t_shift_reg[0]   <= 1'b1;
              t_shift_count    <= 4'b1001; 
              end
            end
         
         //-----------------------------
         // Mode 1
         //-----------------------------
         2'b01 :
            begin
            t_shift_reg[10] <= 1'b1 ; 
            t_shift_reg[9:2] <= sfrdatai ; 
            t_shift_reg[1] <= 1'b0 ; 
            t_shift_reg[0] <= 1'b1 ; 
            t_shift_count <= 4'b1010 ; 
            end
         
         //-----------------------------
         // Mode 2, 3
         //-----------------------------
         default :
            begin
            t_shift_reg[10] <= s0con[3] ; 
            t_shift_reg[9:2] <= sfrdatai ; 
            t_shift_reg[1] <= 1'b0 ; 
            t_shift_reg[0] <= 1'b1 ; 
            t_shift_count <= 4'b1011 ; 
            end
         
         endcase 
         end
      else
         //--------------------------------
         // Transmit register shift
         //--------------------------------
         begin
         if (s0con[7:6] == 2'b00)
            begin
            if (clk_count == 4'b1010)
               begin
               t_shift_reg[9:0] <= t_shift_reg[10:1] ; 
               end 
            end
         else
            begin
            if (t_shift_clk)
               begin
               t_shift_reg[9:0] <= t_shift_reg[10:1] ; 
               end 
            end 
            
         //--------------------------------
         // Transmit data count
         //--------------------------------
         if (t_shift_clk)
            begin
            t_shift_count <= t_shift_count - 1'b1 ; 
            end 
         end 
         
      //--------------------------------
      // Transmit output
      //--------------------------------
      if (t_start | r_start)
         begin
         case (s0con[7:6])
         2'b00 :  // mode 0
            begin
            if (receive | t_start)
               begin
               if (clk_count > 4'b0010 & clk_count < 4'b1001)
                  begin
                  if (~(t_shift_count == 4'b1001))
                     begin
                     txd0 <= 1'b0 ; 
                     end 
                  end
               else
                  begin
                  txd0 <= 1'b1 ; 
                  end 
               end 
            rxd0o <= t_shift_reg[0] ; 
            end
         
         default :  // mode 1,2,3
            begin
            txd0 <= t_shift_reg[0] ; 
            rxd0o <= 1'b1 ; 
            end
         
         endcase 
         end
      else
         begin
         txd0 <= 1'b1 ; 
         rxd0o <= 1'b1 ; 
         end 
      end  
   end 

   //------------------------------------------------------------------
   // Flip-flop on rxd0i input
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : rxd0_inff_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      rxd0_inff <= 1'b1 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      begin
      if (!rxd0i)
         begin
         rxd0_inff <= 1'b0 ; 
         end
      else
         begin
         rxd0_inff <= 1'b1 ; 
         end 
      end  
   end 

   //------------------------------------------------------------------
   // Falling edge detection on the external input rxd0i
   // rxd0_fall is high active during single clk period
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : rxd0_fall_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      rxd0_fall <= 1'b0 ; 
      rxd0_ff <= 1'b0 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      //--------------------------------
      // Falling edge detection
      //--------------------------------
      begin
      if (!rxd0_inff & rxd0_ff)
         begin
         rxd0_fall <= 1'b1 ; 
         end
      else
         begin
         rxd0_fall <= 1'b0 ; 
         end 
      
      //--------------------------------
      // t0 input flip-flop
      //--------------------------------
      rxd0_ff <= rxd0_inff ; 
      
      end  
   end 

   //------------------------------------------------------------------
   // rxd0i input pin falling edge detector
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : rxd0_vec_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      rxd0_vec <= 3'b111 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // RXD vector write
      //--------------------------------
      begin
      if (b_clk)
         begin
         rxd0_vec <= {rxd0_vec[1:0], rxd0_inff} ; 
         end 
         
      //--------------------------------
      // rxd0i pin value
      //--------------------------------
      case (s0con[7:6])
      2'b00 :  // mode 0
         begin
         if (s0con[5])
            begin
            if (clk_count[0]) // bit 0 - osc/2
                              // bit 1 - osc/4