serial0.v

8051的Verilog实现

   // Serial 0 temporary transmit flag
   //------------------------------------------------------------------
   assign ti_spec = ti_spec_tmp | ti_tmp ; 
   
   //------------------------------------------------------------------
   // Serial 0 temporary rb80 bit
   //------------------------------------------------------------------
   assign s0con2_spec = s0con2_spec_tmp | s0con2_tmp ; 

   //------------------------------------------------------------------
   // s0con(0) and s0con(1) interrupt flip-flops 
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : spec_regs_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      ri_spec_tmp <= 1'b0 ; 
      ti_spec_tmp <= 1'b0 ; 
      s0con2_spec_tmp <= 1'b0 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Rising edge detection
      //--------------------------------
      begin
      if (ri_tmp)
         begin
         ri_spec_tmp <= 1'b1 ; 
         end
      else if (cycle == 1)
         begin
         ri_spec_tmp <= 1'b0 ; 
         end 
      if (ti_tmp)
         begin
         ti_spec_tmp <= 1'b1 ; 
         end
      else if (cycle == 1)
         begin
         ti_spec_tmp <= 1'b0 ; 
         end 
      if (s0con2_tmp)
         begin
         s0con2_spec_tmp <= 1'b1 ; 
         end
      else if (cycle == 1)
         begin
         s0con2_spec_tmp <= 1'b0 ; 
         end 
      end  
   end 

   //------------------------------------------------------------------
   // Rising edge detection on the t1ov 
   // t1ov_rise is high active during single clk period
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : t1ov_rise_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      t1ov_rise <= 1'b0 ; 
      t1ov_ff <= 1'b0 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Rising edge detection
      //--------------------------------
      begin
      if (t1ov & !t1ov_ff)
         begin
         t1ov_rise <= 1'b1 ; 
         end
      else
         begin
         t1ov_rise <= 1'b0 ; 
         end 
      //--------------------------------
      // t1ov_rise flip-flop
      //--------------------------------
      t1ov_ff <= t1ov ; 
      end  
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : s0con_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      s0con      <= S0CON_RV ; 
      ri_tmp     <= 1'b0 ; 
      ti_tmp     <= 1'b0 ; 
      s0con2_val <= 1'b0 ; 
      s0con2_tmp <= 1'b0 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Special function register write
      //--------------------------------
      begin
      case (s0con[7:6])
      //----------------------------------
      // Mode 0
      //----------------------------------
      2'b00 :
         begin
         if (clk_count == 4'b1011 &
            receive &
            r_shift_count == 4'b0001)
            begin
            ri_tmp <= 1'b1 ; 
            end
         else
            begin
            ri_tmp <= 1'b0 ; 
            end 
         end
         
      //----------------------------------
      // Modes 1, 2, 3
      //----------------------------------
      default :
         begin
         if (r_start_fall & r_start_ok)
            begin
            s0con2_val <= rxd0_val ; 
            s0con2_tmp <= 1'b1 ; 
            if (s0con[5])
               begin
               ri_tmp <= rxd0_val ; // rec. int. flag 
               end
            else
               begin
               ri_tmp <= 1'b1 ; // rec. int. flag                   
               end 
            end
         else
            begin
            ri_tmp <= 1'b0 ; 
            end 
         end
         
      endcase 
      
      if (t_shift_clk & t_shift_count == 4'b0001)
         begin
         ti_tmp <= 1'b1 ; 
         end
      else
         begin
         ti_tmp <= 1'b0 ; 
         end 
         
      if (sfrwe & sfraddr == S0CON_ID)
         begin
         s0con <= sfrdatai ; 
         end
      else
         begin
         if (ri_spec)
            begin
            s0con[0] <= 1'b1 ; 
            end 
         if (ti_spec)
            begin
            s0con[1] <= 1'b1 ; 
            end 
         if (s0con2_spec)
            begin
            s0con[2] <= s0con2_val ; 
            end 
         end 
      end  
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : s0rell_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      s0rell <= S0RELL_RV ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Special function register write
      //--------------------------------
      begin
      if (sfrwe & sfraddr == S0RELL_ID)
         begin
         s0rell <= sfrdatai ; 
         end 
      end  
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : s0relh_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      s0relh <= S0RELH_RV ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Special function register write
      //--------------------------------
      begin
      if (sfrwe & sfraddr == S0RELH_ID)
         begin
         s0relh <= sfrdatai ; 
         end 
      end  
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : adcon_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      adcon <= ADCON_RV ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Special function register write
      //--------------------------------
      begin
      if (sfrwe & sfraddr == ADCON_ID)
         begin
         adcon <= sfrdatai ; 
         end 
      end  
   end 

   //------------------------------------------------------------------
   // Timer Baud Rate overflow
   // baud_rate_ov is high active during single clk period
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : baud_rate_overflow
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      baud_rate_ov <= 1'b0 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      begin
      if (clk_ov2 & tim_baud[9:0] == 10'b1111111111)
         begin
         baud_rate_ov <= 1'b1 ; 
         end
      else
         begin
         baud_rate_ov <= 1'b0 ; 
         end 
      end  
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : tim_baud_reload
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      tim_baud <= 10'b1111110011 ;  // this value is not specified
                                    // in instruction of SAB80C517   
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      begin
      if (baud_rate_ov)
         begin
         tim_baud[7:0] <= s0rell ; 
         tim_baud[9:8] <= s0relh[1:0] ; 
         end
      else if (!clk_ov2)
         begin
         tim_baud <= tim_baud + 1'b1 ; 
         end 
      end  
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : clk_count_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      clk_count <= 4'b0000 ; 
      clk_ov2 <= 1'b0 ; 
      clk_ov12 <= 1'b0 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // clk counter
      //--------------------------------
      begin
      if (clk_count == 4'b1011)
         begin
         clk_count <= 4'b0000 ; 
         end
      else
         begin
         clk_count <= clk_count + 1'b1 ; 
         end 
         
      //--------------------------------
      // clk divide by 2
      //--------------------------------
      if (clk_count[0])
         begin
         clk_ov2 <= 1'b1 ; 
         end
      else
         begin
         clk_ov2 <= 1'b0 ; 
         end 
      
      //--------------------------------
      // clk divide by 4
      //--------------------------------
      if (clk_count[1:0] == 2'b11)
         begin
         clk_ov4 <= 1'b1 ; 
         end
      else
         begin
         clk_ov4 <= 1'b0 ; 
         end 
      
      //--------------------------------
      // clk divide by 12
      //--------------------------------
      if (clk_count == 4'b1011)
         begin
         clk_ov12 <= 1'b1 ; 
         end
      else
         begin
         clk_ov12 <= 1'b0 ;