alu.v

8051的Verilog实现

                  instr == ORL_A_N | instr == XRL_A_N |
                  instr == ANL_ADDR_N | instr == ORL_ADDR_N |
                  instr == XRL_ADDR_N | instr == CJNE_A_N |
                  instr == CJNE_R0_N | instr == CJNE_R1_N |
                  instr == CJNE_R2_N | instr == CJNE_R3_N |
                  instr == CJNE_R4_N | instr == CJNE_R5_N |
                  instr == CJNE_R6_N | instr == CJNE_R7_N) ? a2
                  : ramsfrdata ; 
   
   //------------------------------------------------------------------
   // Arithmetic-logic machine
   // ALU Carry input
   //------------------------------------------------------------------
   assign op_c = psw[7] ; 

   //------------------------------------------------------------------
   always @(instr or op_a or op_b or op_c)
   begin : combinational_b1_alu_proc
   //------------------------------------------------------------------
   // ---------------------------
   // Initial value
   // ---------------------------
   result_b1 = 9'bXXXXXXXXX;
   ac_bit    = 1'bX;
   ov_bit    = 1'bX;

   // ---------------------------
   // Combinational value
   // ---------------------------
   case (instr[7:0])
   ADD_N,   ADD_ADDR,
   ADD_IR0, ADD_IR1,
   ADD_R0,  ADD_R1,
   ADD_R2,  ADD_R3,
   ADD_R4,  ADD_R5,
   ADD_R6,  ADD_R7 :
      begin
      b1_res_3_0 = {1'b0, op_a[3:0]} + op_b[3:0]; 
      b1_res_6_4 = {1'b0, op_a[6:4]} + op_b[6:4] + b1_res_3_0[4]; 
      b1_res_8_7 = {1'b0, op_a[7]} + op_b[7] + b1_res_6_4[3]; 
      result_b1 = {b1_res_8_7, b1_res_6_4[2:0], b1_res_3_0[3:0]} ; 
      end
         
   ADDC_N,  ADDC_ADDR,
   ADDC_IR0,ADDC_IR1,
   ADDC_R0, ADDC_R1,
   ADDC_R2, ADDC_R3,
   ADDC_R4, ADDC_R5,
   ADDC_R6, ADDC_R7 :
      begin
      b1_res_3_0 = {1'b0, op_a[3:0]} + op_b[3:0] + op_c; 
      b1_res_6_4 = {1'b0, op_a[6:4]} + op_b[6:4] + b1_res_3_0[4]; 
      b1_res_8_7 = {1'b0, op_a[7]} + op_b[7] + b1_res_6_4[3]; 
      result_b1 = {b1_res_8_7, b1_res_6_4[2:0], b1_res_3_0[3:0]} ; 
      end
   
   SUBB_N,  SUBB_ADDR,
   SUBB_IR0,SUBB_IR1,
   SUBB_R0, SUBB_R1,
   SUBB_R2, SUBB_R3,
   SUBB_R4, SUBB_R5,
   SUBB_R6, SUBB_R7 :
      begin
      b1_res_3_0 = {1'b0, op_a[3:0]} - op_b[3:0] - op_c; 
      b1_res_6_4 = {1'b0, op_a[6:4]} - op_b[6:4] - b1_res_3_0[4]; 
      b1_res_8_7 = {1'b0, op_a[7]} - op_b[7] - b1_res_6_4[3]; 
      result_b1 = {b1_res_8_7, b1_res_6_4[2:0], b1_res_3_0[3:0]} ; 
      end
         
   CJNE_A_N,   CJNE_A_ADDR,
   CJNE_R0_N,  CJNE_R1_N,
   CJNE_R2_N,  CJNE_R3_N,
   CJNE_R4_N,  CJNE_R5_N,
   CJNE_R6_N,  CJNE_R7_N :
      begin
      b1_res_3_0 = {1'b0, op_a[3:0]} - op_b[3:0]; 
      b1_res_6_4 = {1'b0, op_a[6:4]} - op_b[6:4] - b1_res_3_0[4]; 
      b1_res_8_7 = {1'b0, op_a[7]} - op_b[7] - b1_res_6_4[3]; 
      result_b1 = {b1_res_8_7, b1_res_6_4[2:0], b1_res_3_0[3:0]} ; 
      end
         
   CJNE_IR0_N, CJNE_IR1_N :
      begin
      b1_res_3_0 = {1'b0, op_b[3:0]} - op_a[3:0]; 
      b1_res_6_4 = {1'b0, op_b[6:4]} - op_a[6:4] - b1_res_3_0[4]; 
      b1_res_8_7 = {1'b0, op_b[7]} - op_a[7] - b1_res_6_4[3]; 
      result_b1 = {b1_res_8_7, b1_res_6_4[2:0], b1_res_3_0[3:0]} ; 
      end
   
   INC_ADDR,INC_IR0,
   INC_IR1, INC_R0,
   INC_R1,  INC_R2,
   INC_R3,  INC_R4,
   INC_R5,  INC_R6,
   INC_R7 :
      begin
      b1_res_3_0 = 5'bXXXXX; 
      b1_res_6_4 = 4'bXXXX; 
      b1_res_8_7 = 2'bXX; 
      result_b1 = {1'b0, op_b} + 1'b1 ; 
      end
   
   INC_A :
      begin
      b1_res_3_0 = 5'bXXXXX; 
      b1_res_6_4 = 4'bXXXX; 
      b1_res_8_7 = 2'bXX; 
      result_b1 = {1'b0, op_a} + 1'b1 ; 
      end
   
   DEC_ADDR,DEC_IR0,
   DEC_IR1, DEC_R0,
   DEC_R1,  DEC_R2,
   DEC_R3,  DEC_R4,
   DEC_R5,  DEC_R6,
   DEC_R7,  DJNZ_R0,
   DJNZ_R1, DJNZ_R2,
   DJNZ_R3, DJNZ_R4,
   DJNZ_R5, DJNZ_R6,
   DJNZ_R7, DJNZ_ADDR :
      begin
      b1_res_3_0 = 5'bXXXXX; 
      b1_res_6_4 = 4'bXXXX; 
      b1_res_8_7 = 2'bXX; 
      result_b1 = {1'b0, op_b} - 1'b1 ; 
      end
   
   DEC_A :
      begin
      b1_res_3_0 = 5'bXXXXX; 
      b1_res_6_4 = 4'bXXXX; 
      b1_res_8_7 = 2'bXX; 
      result_b1 = {1'b0, op_a} - 1'b1 ; 
      end
   
   default :
      begin
      b1_res_3_0 = 5'bXXXXX; 
      b1_res_6_4 = 4'bXXXX; 
      b1_res_8_7 = 2'bXX; 
      result_b1 = 9'bXXXXXXXXX; 
      end
   
   endcase 
   
   ac_bit = b1_res_3_0[4] ; 
   ov_bit = (b1_res_6_4[3] ^ b1_res_8_7[1]) ; 
   end 

   //------------------------------------------------------------------
   always @(instr or op_a or op_b or op_c or psw)
   begin : combinational_b2_alu_proc
   //------------------------------------------------------------------
   // ---------------------------
   // Initial value
   // ---------------------------
   result_b2 = 9'bXXXXXXXXX;
   
   // ---------------------------
   // Combinational value
   // ---------------------------
   case (instr[7:0])
      ORL_ADDR_A, ORL_ADDR_N,
      ORL_A_N, ORL_A_ADDR,
      ORL_A_IR0, ORL_A_IR1,
      ORL_A_R0, ORL_A_R1,
      ORL_A_R2, ORL_A_R3,
      ORL_A_R4, ORL_A_R5,
      ORL_A_R6, ORL_A_R7 :
         begin
         b2_res_3_0 = 5'bXXXXX; 
         b2_res_6_4 = 4'bXXXX; 
         b2_res_8_7 = 2'bXX; 
         result_b2 = {1'b0, (op_a | op_b)} ; 
         end
      
      XRL_ADDR_A, XRL_ADDR_N,
      XRL_A_N, XRL_A_ADDR,
      XRL_A_IR0, XRL_A_IR1,
      XRL_A_R0, XRL_A_R1,
      XRL_A_R2, XRL_A_R3,
      XRL_A_R4, XRL_A_R5,
      XRL_A_R6, XRL_A_R7 :
         begin
         b2_res_3_0 = 5'bXXXXX; 
         b2_res_6_4 = 4'bXXXX; 
         b2_res_8_7 = 2'bXX; 
         result_b2 = {1'b0, (op_a ^ op_b)} ; 
         end
      
      ANL_ADDR_A, ANL_ADDR_N,
      ANL_A_N, ANL_A_ADDR,
      ANL_A_IR0, ANL_A_IR1,
      ANL_A_R0, ANL_A_R1,
      ANL_A_R2, ANL_A_R3,
      ANL_A_R4, ANL_A_R5,
      ANL_A_R6, ANL_A_R7 :
         begin
         b2_res_3_0 = 5'bXXXXX; 
         b2_res_6_4 = 4'bXXXX; 
         b2_res_8_7 = 2'bXX; 
         result_b2 = {1'b0, (op_a & op_b)} ; 
         end
      
      DA_A :
         begin
         if (op_a[3:0] > 4'b1001 | (psw[6]))
            begin
            b2_res_3_0 = {1'b0, op_a[3:0]} + 4'b0110; 
            end
         else
            begin
            b2_res_3_0 = {1'b0, op_a[3:0]}; 
            end 
            
         if (((b2_res_3_0[4]) & op_a[7:4] > 4'b1000) |
            (op_a[7:4] > 4'b1001) |
            (op_c))
            begin
            b2_res_6_4 = {1'b0, op_a[6:4]} + b2_res_3_0[4] + 3'b110; 
            end
         else
            begin
            b2_res_6_4 = {1'b0, op_a[6:4]} + b2_res_3_0[4]; 
            end 
            
         b2_res_8_7 = {1'b0, op_a[7]} + b2_res_6_4[3]; 
         result_b2 = {b2_res_8_7, b2_res_6_4[2:0], b2_res_3_0[3:0]} ; 
         end
      
      CLR_A :
         begin
         b2_res_3_0 = 5'bXXXXX; 
         b2_res_6_4 = 4'bXXXX; 
         b2_res_8_7 = 2'bXX; 
         result_b2 = 9'b000000000 ; 
         end
      
      CPL_A :
         begin
         b2_res_3_0 = 5'bXXXXX; 
         b2_res_6_4 = 4'bXXXX; 
         b2_res_8_7 = 2'bXX; 
         result_b2 = {1'bX, (~op_a)} ; 
         end
      
      RL_A :
         begin
         b2_res_3_0 = 5'bXXXXX; 
         b2_res_6_4 = 4'bXXXX; 
         b2_res_8_7 = 2'bXX; 
         result_b2 = {1'bX, op_a[6:0], op_a[7]} ; 
         end
      
      RR_A :
         begin
         b2_res_3_0 = 5'bXXXXX; 
         b2_res_6_4 = 4'bXXXX; 
         b2_res_8_7 = 2'bXX; 
         result_b2 = {1'bX, op_a[0], op_a[7:1]} ; 
         end
      
      RLC_A :
         begin
         b2_res_3_0 = 5'bXXXXX; 
         b2_res_6_4 = 4'bXXXX; 
         b2_res_8_7 = 2'bXX; 
         result_b2 = {op_a[7:0], psw[7]} ; 
         end
      
      RRC_A :
         begin
         b2_res_3_0 = 5'bXXXXX; 
         b2_res_6_4 = 4'bXXXX; 
         b2_res_8_7 = 2'bXX; 
         result_b2 = {op_a[0], psw[7], op_a[7:1]} ; 
         end
      
      SWAP_A :
         begin
         b2_res_3_0 = 5'bXXXXX; 
         b2_res_6_4 = 4'bXXXX; 
         b2_res_8_7 = 2'bXX; 
         result_b2 = {1'bX, op_a[3:0], op_a[7:4]} ; 
         end
      
      default :
         begin
         b2_res_3_0 = 5'bXXXXX; 
         b2_res_6_4 = 4'bXXXX; 
         b2_res_8_7 = 2'bXX; 
         result_b2 = 9'bXXXXXXXXX; 
         end
      
      endcase 
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : b1_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      b1 <= 8'b00000000 ; 
      end
   else
      begin
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      if (~(instr == DJNZ_ADDR & cycle == 4'b 0011))
         begin
         b1 <= result_b1[7:0] ; 
         end 
      end  
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : b2_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      b2 <= 8'b00000000 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      begin
         b2 <= result_b2[7:0] ; 
      end  
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : bit_nr_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      bit_nr <= 3'b000 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      begin
      case (cycle)
         4'b 0001 :
            begin
            case (instr[7:0])
            CLR_BIT, SETB_BIT,
            ANL_C_BIT, ANL_C_NBIT,
            ORL_C_BIT, ORL_C_NBIT,
            MOV_C_BIT, MOV_BIT_C,
            CPL_BIT, JBC_BIT,
            JB_BIT, JNB_BIT :
               begin
               bit_nr <= memdatai[2:0] ; 
               end
            
            endcase 
            end
         
         endcase 
      end  
   end 
   
   //------------------------------------------------------------------
   // Boolean machine
   // Operand multiplexer
   //------------------------------------------------------------------
   assign bool_op = (instr == CLR_BIT | instr == SETB_BIT |
                     instr == CPL_BIT | instr == MOV_BIT_C)
                     ? ramsfrdata : a1 ; 

   //------------------------------------------------------------------
   // Boolean machine
   // Combinational part
   //------------------------------------------------------------------
   always @(instr or bool_op or psw or bit_nr)
   begin : combinational_boolean_unit_proc
   //------------------------------------------------------------------
   //----------------------------
   // Initial value
   //----------------------------
   bool_res = bool_op[7:0];
   
   //----------------------------
   // Combinational value
   //----------------------------
   case (instr[7:0])