alu.v

8051的Verilog实现

            end
         
         ORL_C_BIT :
            begin
            if (cycle == 4'b 0010 & mempsackint)
               begin
               case (bit_nr)
               3'b000 :
                  begin
                  psw[7] <= psw[7] | ramsfrdata[0] ; 
                  end
               
               3'b001 :
                  begin
                  psw[7] <= psw[7] | ramsfrdata[1] ; 
                  end
               
               3'b010 :
                  begin
                  psw[7] <= psw[7] | ramsfrdata[2] ; 
                  end
               
               3'b011 :
                  begin
                  psw[7] <= psw[7] | ramsfrdata[3] ; 
                  end
               
               3'b100 :
                  begin
                  psw[7] <= psw[7] | ramsfrdata[4] ; 
                  end
               
               3'b101 :
                  begin
                  psw[7] <= psw[7] | ramsfrdata[5] ; 
                  end
               
               3'b110 :
                  begin
                  psw[7] <= psw[7] | ramsfrdata[6] ; 
                  end
               
               default :  // 3'b111
                  begin
                  psw[7] <= psw[7] | ramsfrdata[7] ; 
                  end
               
               endcase 
               end 
            end
         
         ORL_C_NBIT :
            begin
            if (cycle == 4'b 0010 & mempsackint)
               begin
               case (bit_nr)
               3'b000 :
                  begin
                  psw[7] <= psw[7] | ~ramsfrdata[0] ; 
                  end
               
               3'b001 :
                  begin
                  psw[7] <= psw[7] | ~ramsfrdata[1] ; 
                  end
               
               3'b010 :
                  begin
                  psw[7] <= psw[7] | ~ramsfrdata[2] ; 
                  end
               
               3'b011 :
                  begin
                  psw[7] <= psw[7] | ~ramsfrdata[3] ; 
                  end
               
               3'b100 :
                  begin
                  psw[7] <= psw[7] | ~ramsfrdata[4] ; 
                  end
               
               3'b101 :
                  begin
                  psw[7] <= psw[7] | ~ramsfrdata[5] ; 
                  end
               
               3'b110 :
                  begin
                  psw[7] <= psw[7] | ~ramsfrdata[6] ; 
                  end
               
               default :  // 3'b111
                  begin
                  psw[7] <= psw[7] | ~ramsfrdata[7] ; 
                  end
               
               endcase 
               end 
            end
         
         MOV_C_BIT :
            begin
            if (cycle == 4'b 0010 & mempsackint)
               begin
               case (bit_nr)
               3'b000 :
                  begin
                  psw[7] <= ramsfrdata[0] ; 
                  end
               
               3'b001 :
                  begin
                  psw[7] <= ramsfrdata[1] ; 
                  end
               
               3'b010 :
                  begin
                  psw[7] <= ramsfrdata[2] ; 
                  end
               
               3'b011 :
                  begin
                  psw[7] <= ramsfrdata[3] ; 
                  end
               
               3'b100 :
                  begin
                  psw[7] <= ramsfrdata[4] ; 
                  end
               
               3'b101 :
                  begin
                  psw[7] <= ramsfrdata[5] ; 
                  end
               
               3'b110 :
                  begin
                  psw[7] <= ramsfrdata[6] ; 
                  end
               
               default :  // 3'b111
                  begin
                  psw[7] <= ramsfrdata[7] ; 
                  end
               
               endcase 
               end 
            end
         
         endcase 
         //-----------------------------
         // PSW(6) AC FLAG WRITE
         //-----------------------------
         case (instr[7:0])
         ADD_N, ADD_IR0,
         ADD_IR1, ADD_R0,
         ADD_R1, ADD_R2,
         ADD_R3, ADD_R4,
         ADD_R5, ADD_R6,
         ADD_R7, ADDC_N,
         ADDC_IR0, ADDC_IR1,
         ADDC_R0, ADDC_R1,
         ADDC_R2, ADDC_R3,
         ADDC_R4, ADDC_R5,
         ADDC_R6, ADDC_R7,
         SUBB_N, SUBB_IR0,
         SUBB_IR1, SUBB_R0,
         SUBB_R1, SUBB_R2,
         SUBB_R3, SUBB_R4,
         SUBB_R5, SUBB_R6,
         SUBB_R7 :
            begin
            psw[6] <= ac_bit ; 
            end

         ADD_ADDR, ADDC_ADDR,
         SUBB_ADDR :
            begin
            if (cycle == 4'b 0010 & mempsackint)
               begin
               psw[6] <= ac_bit ; 
               end 
            end
         
         endcase 
         
         //-----------------------------
         // PSW(2) OV FLAG WRITE
         //-----------------------------
         case (instr[7:0])
         ADD_N, ADD_IR0,
         ADD_IR1, ADD_R0,
         ADD_R1, ADD_R2,
         ADD_R3, ADD_R4,
         ADD_R5, ADD_R6,
         ADD_R7, ADDC_N,
         ADDC_IR0, ADDC_IR1,
         ADDC_R0, ADDC_R1,
         ADDC_R2, ADDC_R3,
         ADDC_R4, ADDC_R5,
         ADDC_R6, ADDC_R7,
         SUBB_N, SUBB_IR0,
         SUBB_IR1, SUBB_R0,
         SUBB_R1, SUBB_R2,
         SUBB_R3, SUBB_R4,
         SUBB_R5, SUBB_R6,
         SUBB_R7 :
            begin
            psw[2] <= ov_bit ; 
            end
         
         ADD_ADDR, ADDC_ADDR,
         SUBB_ADDR :
            begin
            if (cycle == 4'b 0010 & mempsackint)
               begin
               psw[2] <= ov_bit ; 
               end 
            end
               
         MUL_AB :
            begin
            if (sum1[8:1] == 8'b00000000)
               begin
               psw[2] <= 1'b0 ; 
               end
            else
               begin
               psw[2] <= 1'b1 ; 
               end 
            end
               
         DIV_AB :
            begin
            if (b == 8'b00000000)
               begin
               psw[2] <= 1'b1 ; 
               end
            else
               begin
               psw[2] <= 1'b0 ; 
               end 
            end
         
         endcase 
            
         //-----------------------------
         // PSW(0) P FLAG WRITE
         //-----------------------------
         psw[0] <= parity_bit ; 
         
         end 
      end  
   end 
   
   //------------------------------------------------------------------
   // Parity bit driver
   //------------------------------------------------------------------
   assign parity_bit = (acc[0] ^ acc[1] ^ acc[2] ^ acc[3] ^
      acc[4] ^ acc[5] ^ acc[6] ^ acc[7]) ; 

   //------------------------------------------------------------------
   // Arithmetic-logic machine
   // Operand 1 register
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : a1_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      a1 <= 8'b00000000 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      begin
      case (cycle)
      4'b 0001 :
         begin
         case (instr[7:0])
         CJNE_R0_N, CJNE_R1_N,
         CJNE_R2_N, CJNE_R3_N,
         CJNE_R4_N, CJNE_R5_N,
         CJNE_R6_N, CJNE_R7_N,
         XCH_R0, XCH_R1,
         XCH_R2, XCH_R3,
         XCH_R4, XCH_R5,
         XCH_R6, XCH_R7 :
            begin
            a1 <= ramsfrdata ; 
            end
         
         CJNE_IR0_N, CJNE_IR1_N :
            begin
            a1 <= memdatai ; 
            end
         
         endcase 
         end
      4'b 0010 :
         begin
         case (instr[7:0])
         CLR_BIT, SETB_BIT,
         ANL_C_BIT, ANL_C_NBIT,
         ORL_C_BIT, ORL_C_NBIT,
         MOV_C_BIT, MOV_BIT_C,
         CPL_BIT, JBC_BIT,
         JB_BIT, JNB_BIT,
         ANL_ADDR_N, ORL_ADDR_N,
         XRL_ADDR_N, XCH_ADDR,
         XCH_IR0, XCH_IR1 :
            begin
            a1 <= ramsfrdata ; 
            end
         
         endcase 
         end
      endcase 
      end  
   end 

   //------------------------------------------------------------------
   // Arithmetic-logic machine
   // Operand 2 register
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : a2_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      a2 <= 8'b00000000 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      begin
      case (cycle)
      4'b 0001 :
         begin
         case (instr[7:0])
         ADD_N, ADDC_N,
         SUBB_N, ANL_A_N,
         ORL_A_N, XRL_A_N,
         CJNE_A_N, CJNE_R0_N,
         CJNE_R1_N, CJNE_R2_N,
         CJNE_R3_N, CJNE_R4_N,
         CJNE_R5_N, CJNE_R6_N,
         CJNE_R7_N :
            begin
            a2 <= memdatai ; 
            end
         
         endcase 
         end
      4'b 0010 :
         begin
         case (instr[7:0])
         ANL_ADDR_N, ORL_ADDR_N,
         XRL_ADDR_N :
            begin
            a2 <= memdatai ; 
            end
         
         ANL_ADDR_A, ORL_ADDR_A,
         XRL_ADDR_A, CJNE_A_ADDR :
            begin
            a2 <= ramsfrdata ; 
            end
         
         endcase 
         end
      
      endcase 
      end  
   end 
   
   //------------------------------------------------------------------
   // Arithmetic-logic machine
   // ALU Operand 1 input
   //------------------------------------------------------------------
   assign op_a = (instr == ANL_ADDR_N | instr == ORL_ADDR_N |
                  instr == XRL_ADDR_N | instr == CJNE_R0_N |
                  instr == CJNE_R1_N | instr == CJNE_R2_N |
                  instr == CJNE_R3_N | instr == CJNE_R4_N |
                  instr == CJNE_R5_N | instr == CJNE_R6_N |
                  instr == CJNE_R7_N | instr == CJNE_IR0_N |
                  instr == CJNE_IR1_N) ? a1 : acc ; 
   
   //------------------------------------------------------------------
   // Arithmetic-logic machine
   // ALU Operand 2 input
   //------------------------------------------------------------------
   assign op_b = (instr == ADD_N | instr == ADDC_N |
                  instr == SUBB_N | instr == ANL_A_N |