📄 alu.v
字号:
end
end
ORL_A_R0, ORL_A_R1,
ORL_A_R2, ORL_A_R3,
ORL_A_R4, ORL_A_R5,
ORL_A_R6, ORL_A_R7,
ANL_A_R0, ANL_A_R1,
ANL_A_R2, ANL_A_R3,
ANL_A_R4, ANL_A_R5,
ANL_A_R6, ANL_A_R7,
XRL_A_R0, XRL_A_R1,
XRL_A_R2, XRL_A_R3,
XRL_A_R4, XRL_A_R5,
XRL_A_R6, XRL_A_R7,
DA_A, CLR_A, CPL_A,
RL_A, RR_A, RLC_A,
RRC_A, SWAP_A :
begin
if (mempsackint)
begin
acc <= result_b2[7:0] ;
end
end
MOV_A_R0, MOV_A_R1,
MOV_A_R2, MOV_A_R3,
MOV_A_R4, MOV_A_R5,
MOV_A_R6, MOV_A_R7 :
begin
if (mempsackint)
begin
acc <= ramsfrdata[7:0] ;
end
end
endcase
end
4'b 0010 :
begin
case (instr[7:0])
ADD_N, ADD_ADDR,
ADD_IR0, ADD_IR1,
ADDC_N, ADDC_ADDR,
ADDC_IR0, ADDC_IR1,
SUBB_N, SUBB_ADDR,
SUBB_IR0, SUBB_IR1 :
begin
if (mempsackint)
begin
acc <= result_b1[7:0] ;
end
end
ANL_A_N, ANL_A_ADDR,
ANL_A_IR0, ANL_A_IR1,
ORL_A_N, ORL_A_ADDR,
ORL_A_IR0, ORL_A_IR1,
XRL_A_N, XRL_A_ADDR,
XRL_A_IR0, XRL_A_IR1 :
begin
if (mempsackint)
begin
acc <= result_b2[7:0] ;
end
end
MOV_A_N :
begin
if (mempsackint)
begin
acc <= sfrdatai[7:0] ;
end
end
// DR (SFR write)
MOV_A_ADDR, MOV_A_IR0,
MOV_A_IR1 :
begin
if (mempsackint)
begin
acc <= ramsfrdata ;
end
end
// RAM,SFR read
XCH_R0, XCH_R1,
XCH_R2, XCH_R3,
XCH_R4, XCH_R5,
XCH_R6, XCH_R7 :
begin
if (mempsackint)
begin
acc <= a1 ;
end
end
XCHD_IR0, XCHD_IR1 :
begin
acc[3:0] <= ramsfrdata[3:0] ;
end
// databus -- RAM read
endcase
end
4'b 0011 :
begin
case (instr[7:0])
XCH_ADDR, XCH_IR0,
XCH_IR1 :
begin
acc <= a1 ;
end
endcase
end
4'b 0101 :
begin
case (instr[7:0])
MUL_AB :
begin
if (mempsackint)
begin
acc <= {sum1[0], sum[0], mda[7:2]} ;
end
end
DIV_AB :
begin
if (mempsackint)
begin
acc <= {mda[5:0], sum[8], sum1[8]} ;
end
end
endcase
end
endcase
end
end
end
//------------------------------------------------------------------
// B register
//------------------------------------------------------------------
always @(posedge clk)
begin : b_write_proc
//------------------------------------------------------------------
if (rst)
begin
//-----------------------------------
// Synchronous reset
//-----------------------------------
b <= B_RV ;
end
else
begin
//-----------------------------------
// Synchronous write
//-----------------------------------
// Special function register write
//-----------------------------------
if (sfrwe & sfraddr == B_ID)
begin
b <= sfrdatai ;
end
else
//--------------------------------
// b register operation write
//--------------------------------
begin
case (cycle)
4'b 0101 :
begin
case (instr[7:0])
MUL_AB :
begin
if (mempsackint)
begin
b <= sum1[8:1] ;
end
end
DIV_AB :
begin
if (mempsackint)
begin
if (sum1[8])
begin
b <= sum1[7:0] ;
end
else if (sum[8])
begin
b <= {sum[6:0], mda[7]} ;
end
else
begin
b <= {mdb[6:0], mda[7]} ;
end
end
end
endcase
end
endcase
end
end
end
//------------------------------------------------------------------
// PSW register
//------------------------------------------------------------------
always @(posedge clk)
begin : psw_write_proc
//------------------------------------------------------------------
if (rst)
begin
//-----------------------------------
// Synchronous reset
//-----------------------------------
psw <= PSW_RV ;
end
else
begin
//-----------------------------------
// Synchronous write
//-----------------------------------
// Special function register write
//-----------------------------------
if (sfrwe & sfraddr == PSW_ID)
begin
psw <= sfrdatai ;
end
else
//-----------------------------
// PSW(7) CY FLAG WRITE
//-----------------------------
begin
case (instr[7:0])
ADD_N, ADD_IR0,
ADD_IR1, ADD_R0,
ADD_R1, ADD_R2,
ADD_R3, ADD_R4,
ADD_R5, ADD_R6,
ADD_R7, ADDC_R0,
ADDC_R1, ADDC_R2,
ADDC_R3, ADDC_R4,
ADDC_R5, ADDC_R6,
ADDC_R7, SUBB_R0,
SUBB_R1, SUBB_R2,
SUBB_R3, SUBB_R4,
SUBB_R5, SUBB_R6,
SUBB_R7, CJNE_R0_N,
CJNE_R1_N, CJNE_R2_N,
CJNE_R3_N, CJNE_R4_N,
CJNE_R5_N, CJNE_R6_N,
CJNE_R7_N, CJNE_A_N :
begin
if (mempsackint)
begin
psw[7] <= result_b1[8] ;
end
end
RLC_A, RRC_A :
begin
if (mempsackint)
begin
psw[7] <= result_b2[8] ;
end
end
ADD_ADDR, ADDC_ADDR,
ADDC_IR0, ADDC_IR1,
ADDC_N, SUBB_N,
SUBB_ADDR, CJNE_A_ADDR,
CJNE_IR0_N, CJNE_IR1_N,
SUBB_IR0, SUBB_IR1 :
begin
if (cycle == 4'b 0010 & mempsackint)
begin
psw[7] <= result_b1[8] ;
end
end
DA_A :
begin
if (result_b2[8] & mempsackint)
begin
psw[7] <= 1'b1 ;
end
end
MUL_AB, DIV_AB,
CLR_C :
begin
psw[7] <= 1'b0 ;
end
SETB_C :
begin
psw[7] <= 1'b1 ;
end
CPL_C :
begin
if (mempsackint)
begin
psw[7] <= ~psw[7] ;
end
end
ANL_C_BIT :
begin
if (cycle == 4'b 0010 & mempsackint)
begin
case (bit_nr)
3'b000 :
begin
psw[7] <= psw[7] & ramsfrdata[0] ;
end
3'b001 :
begin
psw[7] <= psw[7] & ramsfrdata[1] ;
end
3'b010 :
begin
psw[7] <= psw[7] & ramsfrdata[2] ;
end
3'b011 :
begin
psw[7] <= psw[7] & ramsfrdata[3] ;
end
3'b100 :
begin
psw[7] <= psw[7] & ramsfrdata[4] ;
end
3'b101 :
begin
psw[7] <= psw[7] & ramsfrdata[5] ;
end
3'b110 :
begin
psw[7] <= psw[7] & ramsfrdata[6] ;
end
default : // 3'b111
begin
psw[7] <= psw[7] & ramsfrdata[7] ;
end
endcase
end
end
ANL_C_NBIT :
begin
if (cycle == 4'b 0010 & mempsackint)
begin
case (bit_nr)
3'b000 :
begin
psw[7] <= psw[7] & ~ramsfrdata[0] ;
end
3'b001 :
begin
psw[7] <= psw[7] & ~ramsfrdata[1] ;
end
3'b010 :
begin
psw[7] <= psw[7] & ~ramsfrdata[2] ;
end
3'b011 :
begin
psw[7] <= psw[7] & ~ramsfrdata[3] ;
end
3'b100 :
begin
psw[7] <= psw[7] & ~ramsfrdata[4] ;
end
3'b101 :
begin
psw[7] <= psw[7] & ~ramsfrdata[5] ;
end
3'b110 :
begin
psw[7] <= psw[7] & ~ramsfrdata[6] ;
end
default : // 3'b111
begin
psw[7] <= psw[7] & ~ramsfrdata[7] ;
end
endcase
end
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -