timer.v

8051的Verilog实现

      //--------------------------------
      // Clock divided by 12
      //--------------------------------
      if (clk_count == 4'b1011)
         begin
         clk_ov12 <= 1'b1 ; 
         end
      else
         begin
         clk_ov12 <= 1'b0 ; 
         end 
      
      end  
   end 
   
   //------------------------------------------------------------------
   // Timer 0 clock
   // t0_clk is high active during single clk period
   //------------------------------------------------------------------
   assign t0_clk = clk_ov12 ; 
   
   //------------------------------------------------------------------
   // Timer 1 clock
   // t1_clk is high active during single clk period
   //------------------------------------------------------------------
   assign t1_clk = clk_ov12 ; 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : t0_ff_proc
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      if (rst)
      begin
         t0_ff0 <= 1'b0 ; 
         t0_ff <= 1'b0 ; 
      end
      else
      begin
         //-----------------------------------
         // Synchronous write
         //-----------------------------------
         // t0 input flip-flop
         //--------------------------------
         t0_ff0 <= t0 ; 
         t0_ff <= t0_ff0 ; 
      end  
   end 
   
   //------------------------------------------------------------------
   // Falling edge detection on the external input t0
   // t0_fall is high active during single clk period
   //------------------------------------------------------------------
   assign t0_fall = t0_ff & ~t0_ff0 ; 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : t1_fall_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      t1_ff0 <= 1'b0 ; 
      t1_ff <= 1'b0 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // t1 input flip-flop
      //--------------------------------
      begin
      t1_ff0 <= t1 ; 
      t1_ff <= t1_ff0 ; 
      end  
   end 
   
   //------------------------------------------------------------------
   // Falling edge detection on the external input t1
   // t1_fall is high active during single clk period
   //------------------------------------------------------------------
   assign t1_fall = t1_ff & ~t1_ff0 ; 

   //------------------------------------------------------------------
   // Falling edge or low level detection on the external input int0
   // int0_fall is high active during single clk period
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : int0_fall_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      int0_fall <= 1'b0 ; 
      int0_ff <= 1'b0 ; 
      int0_ff0  <= 1'b0;
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      //--------------------------------
      // Falling edge detection
      //--------------------------------
      begin
      if (cycle == 1)
         begin
         int0_fall <= 1'b0 ; 
         end
      else if (!int0_ff0 & int0_ff)
         begin
         int0_fall <= 1'b1 ; 
         end 
      
      //--------------------------------
      // int0 input flip-flop
      //--------------------------------
      int0_ff0 <= int0;
      int0_ff  <= int0_ff0;
      
      end  
   end 

   //------------------------------------------------------------------
   // Falling edge or low level detection on the external input int1
   // int1_fall is high active
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : int1_fall_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      int1_fall <= 1'b0 ; 
      int1_ff <= 1'b0 ; 
      int1_ff0  <= 1'b0;
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Falling edge detection
      //--------------------------------
      begin
      if (cycle == 1)
         begin
         int1_fall <= 1'b0 ; 
         end
      else if (!int1_ff0 & int1_ff)
         begin
         int1_fall <= 1'b1 ; 
         end 
      
      //--------------------------------
      // int1 input flip-flop
      //--------------------------------
      int1_ff0 <= int1;
      int1_ff  <= int1_ff0;
      
      end  
   end 
   
   //------------------------------------------------------------------
   // Timer 0 open gate control
   //------------------------------------------------------------------
   assign t0_open = tcon[4] & (int0_ff0 | ~tmod[3]) ; 
   
   //------------------------------------------------------------------
   // Timer 1 open gate control
   //------------------------------------------------------------------
   assign t1_open = tcon[6] & (int1_ff0 | ~tmod[7]) ; 
   
   //------------------------------------------------------------------
   // Timer 0 low ordered byte clock
   // tl0_clk is high active during single clk period
   //------------------------------------------------------------------
   assign tl0_clk =
      (t0_open & !(tmod[2])) ? t0_clk :
      (t0_open & (tmod[2])) ? t0_fall :
      1'b0 ; 
   
   //------------------------------------------------------------------
   // Timer 1 low ordered byte clock
   // tl0_clk is high active during single clk period
   //------------------------------------------------------------------
   assign tl1_clk =
      (t1_open & !(tmod[6]) & ~(t0_mode == 2'b11)) ? t1_clk :
      (t1_open &  (tmod[6]) & ~(t0_mode == 2'b11)) ? t1_fall :
      1'b0 ; 
   
   //------------------------------------------------------------------
   // Timer 0 high ordered byte clock
   // th0_clk is high active during single clk period
   //------------------------------------------------------------------
   assign th0_clk =
      (t0_mode == 2'b00 | t0_mode == 2'b01) ? tl0_ov : // Modes 0 or 1
      ((tcon[6]) & t0_mode == 2'b11) ? t0_clk :        // Mode 3
      1'b0 ; 
   
   //------------------------------------------------------------------
   // Timer 1 high ordered byte clock
   // th1_clk is high active during single clk period
   //------------------------------------------------------------------
   assign th1_clk =
      (t0_mode == 2'b00 | t0_mode == 2'b01) ? tl1_ov : // Modes 0 or 1
      1'b0 ; 

   //------------------------------------------------------------------
   // Timer low 0 overflow
   // tl0_ov is high active during single clk period
   //------------------------------------------------------------------
   assign tl0_ov =
      (
         (tl0[4:0] == 5'b11111 & t0_mode == 2'b00) |
         (tl0[7:0] == 8'b11111111)
      ) ? tl0_clk :
      1'b0 ; 
   
   //------------------------------------------------------------------
   // Timer low 0 overflow flip-flop
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : tl0_ov_ff_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      tl0_ov_ff<= 1'b0;
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      begin
      if (tl0_ov)
         begin
         tl0_ov_ff <= 1'b1;
         end
      else if (cycle == 1)
         begin
         tl0_ov_ff <= 1'b0;
         end
      end
   end

   //------------------------------------------------------------------
   // Timer low 1 overflow
   // tl1_ov is high active during single clk period
   //------------------------------------------------------------------
   assign tl1_ov =
      (
         (tl1[4:0] == 5'b11111 & t1_mode == 2'b00) |
         (tl1[7:0] == 8'b11111111)
      ) ? tl1_clk :
      1'b0 ; 
   
   //------------------------------------------------------------------
   // Timer low 1 overflow flip-flop
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : tl1_ov_ff_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      tl1_ov_ff <= 1'b0 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      begin
      if (tl1_ov)
         begin
         tl1_ov_ff <= 1'b1 ; 
         end
      else if (cycle == 1)
         begin
         tl1_ov_ff <= 1'b0 ; 
         end 
      end  
   end 
   
   //------------------------------------------------------------------
   // Timer high 0 overflow
   // th0_ov is high active during single clk period
   //------------------------------------------------------------------
   assign th0_ov =
      (th0[7:0] == 8'b11111111) ? th0_clk :
      1'b0 ; 
   
   //------------------------------------------------------------------
   // Timer high 0 overflow flip-flop
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : th0_ov_ff_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      th0_ov_ff <= 1'b0 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      begin
      if (th0_ov)
         begin
         th0_ov_ff <= 1'b1 ; 
         end
      else if (cycle == 1)
         begin
         th0_ov_ff <= 1'b0 ; 
         end 
      end  
   end 
   
   //------------------------------------------------------------------
   // Timer high 0 overflow
   // th1_ov is high active during single clk period
   //------------------------------------------------------------------
   assign th1_ov =
      (th1[7:0] == 8'b11111111) ? th1_clk :
      1'b0 ; 
   
   //------------------------------------------------------------------
   // Timer high 1 overflow flip-flop
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : th1_ov_ff_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      th1_ov_ff <= 1'b0 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      begin
      if (th1_ov)
         begin
         th1_ov_ff <= 1'b1 ; 
         end
      else if (cycle == 1)
         begin
         th1_ov_ff <= 1'b0 ; 
         end 
      end  
   end 
   
   //------------------------------------------------------------------
   // Special Function registers read
   //------------------------------------------------------------------
   assign sfrdatatim =
      (sfraddr == TL0_ID) ? tl0 :
      (sfraddr == TH0_ID) ? th0 :
      (sfraddr == TL1_ID) ? tl1 :
      (sfraddr == TH1_ID) ? th1 :
      (sfraddr == TMOD_ID) ? tmod :
      (sfraddr == TCON_ID) ? tcon :
      "--------" ; 


endmodule  //  module TIMER_0_1

//*******************************************************************--