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iex5_ff <= 1'b0 ;
end
else
//-----------------------------------
// Synchronous write
//-----------------------------------
begin
if (cycle == 1 | ~(ccen54_ff == ccen54)) // compare <-> int5 switch
begin
iex5_ff <= 1'b0 ;
end
else if (int5_p1 & !int5_p2) // positive edge
begin
iex5_ff <= 1'b1 ;
end
end
end
//------------------------------------------------------------------
assign iex5 = (~(ccen54_ff == ccen54)) ? 1'b0 // compare <-> int4 switch
: (int5_p1 & ~int5_p2) | iex5_ff ; // positive edge
//------------------------------------------------------------------
always @(posedge clk)
begin : iex6_ff_write_proc
//------------------------------------------------------------------
if (rst)
//-----------------------------------
// Synchronous reset
//-----------------------------------
begin
iex6_ff <= 1'b0 ;
end
else
//-----------------------------------
// Synchronous write
//-----------------------------------
begin
if (cycle == 1 | ~(ccen76_ff == ccen76)) // compare <-> int6 switch
begin
iex6_ff <= 1'b0 ;
end
else if (int6_p1 & !int6_p2) // positive edge
begin
iex6_ff <= 1'b1 ;
end
end
end
//------------------------------------------------------------------
assign iex6 = (~(ccen76_ff == ccen76)) ? 1'b0 // compare <-> int4 switch
: (int6_p1 & ~int6_p2) | iex6_ff ; // positive edge
//------------------------------------------------------------------
always @(posedge clk)
begin : ccen_ff_proc
//------------------------------------------------------------------
if (rst)
//-----------------------------------
// Synchronous reset
//-----------------------------------
begin
ccen76_ff <= 1'b0 ;
ccen54_ff <= 1'b0 ;
ccen32_ff <= 1'b0 ;
ccen10_ff <= 1'b0 ;
end
else
begin
//-----------------------------------
// Synchronous write
//-----------------------------------
ccen76_ff <= ccen76 ;
ccen54_ff <= ccen54 ;
ccen32_ff <= ccen32 ;
ccen10_ff <= ccen10 ;
end
end
//------------------------------------------------------------------
assign ccen76 = (ccenreg[7:6] == 2'b10) ? 1'b1 : 1'b0 ;
//------------------------------------------------------------------
assign ccen54 = (ccenreg[5:4] == 2'b10) ? 1'b1 : 1'b0 ;
//------------------------------------------------------------------
assign ccen32 = (ccenreg[3:2] == 2'b10) ? 1'b1 : 1'b0 ;
//------------------------------------------------------------------
assign ccen10 = (ccenreg[1:0] == 2'b10) ? 1'b1 : 1'b0 ;
//------------------------------------------------------------------
// Mask and priority encode
// level0 - low priority
// level3 - high priority
//------------------------------------------------------------------
always @(ip0 or ip1 or ie0_en or riti1_en or iadc_en or tf0_en or
iex2_en or ie1_en or iex3_en or tf1_en or iex4_en or riti0_en or
iex5_en or tfexf2_en or iex6_en)
begin : mask_proc
//------------------------------------------------------------------
//-----------------------------------
// External interrupt 0
//-----------------------------------
ie0_l3 = ie0_en & ip1[0] & ip0[0] ; // level3
ie0_l2 = ie0_en & ip1[0] & ~ip0[0] ; // level2
ie0_l1 = ie0_en & ~ip1[0] & ip0[0] ; // level1
ie0_l0 = ie0_en & ~ip1[0] & ~ip0[0] ; // level0
//-----------------------------------
// Serial port 1 interrupt
//-----------------------------------
riti1_l3 = riti1_en & ip1[0] & ip0[0] ; // level3
riti1_l2 = riti1_en & ip1[0] & ~ip0[0] ; // level2
riti1_l1 = riti1_en & ~ip1[0] & ip0[0] ; // level1
riti1_l0 = riti1_en & ~ip1[0] & ~ip0[0] ; // level0
//-----------------------------------
// Aanalog - Digital converter interrupt
//-----------------------------------
iadc_l3 = iadc_en & ip1[0] & ip0[0] ; // level3
iadc_l2 = iadc_en & ip1[0] & ~ip0[0] ; // level2
iadc_l1 = iadc_en & ~ip1[0] & ip0[0] ; // level1
iadc_l0 = iadc_en & ~ip1[0] & ~ip0[0] ; // level0
//-----------------------------------
// Timer 0 overflow interrupt
//-----------------------------------
tf0_l3 = tf0_en & ip1[1] & ip0[1] ; // level3
tf0_l2 = tf0_en & ip1[1] & ~ip0[1] ; // level2
tf0_l1 = tf0_en & ~ip1[1] & ip0[1] ; // level1
tf0_l0 = tf0_en & ~ip1[1] & ~ip0[1] ; // level0
//-----------------------------------
// External interrupt 2
//-----------------------------------
iex2_l3 = iex2_en & ip1[1] & ip0[1] ; // level3
iex2_l2 = iex2_en & ip1[1] & ~ip0[1] ; // level2
iex2_l1 = iex2_en & ~ip1[1] & ip0[1] ; // level1
iex2_l0 = iex2_en & ~ip1[1] & ~ip0[1] ; // level0
//-----------------------------------
// External interrupt 1
//-----------------------------------
ie1_l3 = ie1_en & ip1[2] & ip0[2] ; // level3
ie1_l2 = ie1_en & ip1[2] & ~ip0[2] ; // level2
ie1_l1 = ie1_en & ~ip1[2] & ip0[2] ; // level1
ie1_l0 = ie1_en & ~ip1[2] & ~ip0[2] ; // level0
//-----------------------------------
// External interrupt 3
//-----------------------------------
iex3_l3 = iex3_en & ip1[2] & ip0[2] ; // level3
iex3_l2 = iex3_en & ip1[2] & ~ip0[2] ; // level2
iex3_l1 = iex3_en & ~ip1[2] & ip0[2] ; // level1
iex3_l0 = iex3_en & ~ip1[2] & ~ip0[2] ; // level0
//-----------------------------------
// Timer 1 overflow interrupt
//-----------------------------------
tf1_l3 = tf1_en & ip1[3] & ip0[3] ; // level3
tf1_l2 = tf1_en & ip1[3] & ~ip0[3] ; // level2
tf1_l1 = tf1_en & ~ip1[3] & ip0[3] ; // level1
tf1_l0 = tf1_en & ~ip1[3] & ~ip0[3] ; // level0
//-----------------------------------
// External interrupt 4
//-----------------------------------
iex4_l3 = iex4_en & ip1[3] & ip0[3] ; // level3
iex4_l2 = iex4_en & ip1[3] & ~ip0[3] ; // level2
iex4_l1 = iex4_en & ~ip1[3] & ip0[3] ; // level1
iex4_l0 = iex4_en & ~ip1[3] & ~ip0[3] ; // level0
//-----------------------------------
// Serial port 0 interrupt
//-----------------------------------
riti0_l3 = riti0_en & ip1[4] & ip0[4] ; // level3
riti0_l2 = riti0_en & ip1[4] & ~ip0[4] ; // level2
riti0_l1 = riti0_en & ~ip1[4] & ip0[4] ; // level1
riti0_l0 = riti0_en & ~ip1[4] & ~ip0[4] ; // level0
//-----------------------------------
// External interrupt 5
//-----------------------------------
iex5_l3 = iex5_en & ip1[4] & ip0[4] ; // level3
iex5_l2 = iex5_en & ip1[4] & ~ip0[4] ; // level2
iex5_l1 = iex5_en & ~ip1[4] & ip0[4] ; // level1
iex5_l0 = iex5_en & ~ip1[4] & ~ip0[4] ; // level0
//-----------------------------------
// Timer 2 interrupt
//-----------------------------------
tfexf2_l3 = tfexf2_en & ip1[5] & ip0[5] ; //level3
tfexf2_l2 = tfexf2_en & ip1[5] & ~ip0[5] ; //level2
tfexf2_l1 = tfexf2_en & ~ip1[5] & ip0[5] ; //level1
tfexf2_l0 = tfexf2_en & ~ip1[5] & ~ip0[5] ; //level0
//-----------------------------------
// External interrupt 6
//-----------------------------------
iex6_l3 = iex6_en & ip1[5] & ip0[5] ; // level3
iex6_l2 = iex6_en & ip1[5] & ~ip0[5] ; // level2
iex6_l1 = iex6_en & ~ip1[5] & ip0[5] ; // level1
iex6_l0 = iex6_en & ~ip1[5] & ~ip0[5] ; // level0
end
//------------------------------------------------------------------
always @(ien0 or ien1 or ien2 or ircon or ri0 or ti0 or ri1 or
ti1 or ie0 or tf0 or ie1 or tf1)
//------------------------------------------------------------------
begin : priority_encode_proc
//-----------------------------------
// External interrupt 0
//-----------------------------------
ie0_en = ie0 & ien0[7] & ien0[0] ; // interrupt enable
//-----------------------------------
// Serial port 1 interrupt
//-----------------------------------
riti1_en = (ri1 | ti1) & ien0[7] & ien2[0] ; // i.enable
//-----------------------------------
// Aanalog - Digital converter interrupt
//-----------------------------------
iadc_en = ircon[0] & ien0[7] & ien1[0] ; // i. enable
//-----------------------------------
// Timer 0 overflow interrupt
//-----------------------------------
tf0_en = tf0 & ien0[7] & ien0[1] ; // interrupt enable
//-----------------------------------
// External interrupt 2
//-----------------------------------
iex2_en = ircon[1] & ien0[7] & ien1[1] ; // i. enable
//-----------------------------------
// External interrupt 1
//-----------------------------------
ie1_en = ie1 & ien0[7] & ien0[2] ; // interrupt enable
//-----------------------------------
// External interrupt 3
//-----------------------------------
iex3_en = ircon[2] & ien0[7] & ien1[2] ; // i. enable
//-----------------------------------
// Timer 1 overflow interrupt
//-----------------------------------
tf1_en = tf1 & ien0[7] & ien0[3] ; // interrupt enable
//-----------------------------------
// External interrupt 4
//-----------------------------------
iex4_en = ircon[3] & ien0[7] & ien1[3] ; // i. enable
//-----------------------------------
// Serial port 0 interrupt
//-----------------------------------
riti0_en = (ri0 | ti0) & ien0[7] & ien0[4] ; // i.enable
//-----------------------------------
// External interrupt 5
//-----------------------------------
iex5_en = ircon[4] & ien0[7] & ien1[4] ; // i. enable
//-----------------------------------
// Timer 2 interrupt
//-----------------------------------
tfexf2_en = (ircon[7] | ircon[6]) & ien0[7] & ien0[5] ;
//-----------------------------------
// External interrupt 6
//-----------------------------------
iex6_en = ircon[5] & ien0[7] & ien1[5] ; // i. enable
end
//------------------------------------------------------------------
// Interrupt levels
//------------------------------------------------------------------
assign l3 = (ie0_l3 | riti1_l3 | iadc_l3 | tf0_l3 |
iex2_l3 | ie1_l3 | iex3_l3 | tf1_l3 |
iex4_l3 | riti0_l3 | iex5_l3 | tfexf2_l3 |
iex6_l3) ;
//------------------------------------------------------------------
assign l2 = (ie0_l2 | riti1_l2 | iadc_l2 | tf0_l2 |
iex2_l2 | ie1_l2 | iex3_l2 | tf1_l2 |
iex4_l2 | riti0_l2 | iex5_l2 | tfexf2_l2 |
iex6_l2) ;
//------------------------------------------------------------------
assign l1 = (ie0_l1 | riti1_l1 | iadc_l1 | tf0_l1 |
iex2_l1 | ie1_l1 | iex3_l1 | tf1_l1 |
iex4_l1 | riti0_l1 | iex5_l1 | tfexf2_l1 |
iex6_l1) ;
//------------------------------------------------------------------
assign l0 = (ie0_l0 | riti1_l0 | iadc_l0 | tf0_l0 |
iex2_l0 | ie1_l0 | iex3_l0 | tf1_l0 |
iex4_l0 | riti0_l0 | iex5_l0 | tfexf2_l0 |
iex6_l0) ;
//-------------------------------------------------------------------
// Interrupt vector
//-------------------------------------------------------------------
assign ie0_p1 =
((ie0_l3) |
(ie0_l2 & ~l3) |
(ie0_l1 & ~l3 & ~l2) |
(ie0_l0 & ~l3 & ~l2 & ~l1)) ;
//-------------------------------------------------------------------
assign riti1_p1 =
((riti1_l3) |
(riti1_l2 & ~l3) |
(riti1_l1 & ~l3 & ~l2) |
(riti1_l0 & ~l3 & ~l2 & ~l1)) ;
//-------------------------------------------------------------------
assign iadc_p1 =
((iadc_l3) |
(iadc_l2 & ~l3) |
(iadc_l1 & ~l3 & ~l2) |
(iadc_l0 & ~l3 & ~l2 & ~l1)) ;
//-------------------------------------------------------------------
assign tf0_p1 =
((tf0_l3) |
(tf0_l2 & ~l3) |
(tf0_l1 & ~l3 & ~l2) |
(tf0_l0 & ~l3 & ~l2 & ~l1)) ;
//-------------------------------------------------------------------
assign iex2_p1 =
((iex2_l3) |
(iex2_l2 & ~l3) |
(iex2_l1 & ~l3 & ~l2) |
(iex2_l0 & ~l3 & ~l2 & ~l1)) ;
//-------------------------------------------------------------------
assign ie1_p1 =
((ie1_l3) |
(ie1_l2 & ~l3) |
(ie1_l1 & ~l3 & ~l2) |
(ie1_l0 & ~l3 & ~l2 & ~l1)) ;
//-------------------------------------------------------------------
assign iex3_p1 =
((iex3_l3) |
(iex3_l2 & ~l3) |
(iex3_l1 & ~l3 & ~l2) |
(iex3_l0 & ~l3 & ~l2 & ~l1)) ;
//-------------------------------------------------------------------
assign tf1_p1 =
((tf1_l3) |
(tf1_l2 & ~l3) |
(tf1_l1 & ~l3 & ~l2) |
(tf1_l0 & ~l3 & ~l2 & ~l1)) ;
//-------------------------------------------------------------------
assign iex4_p1 =
((iex4_l3) |
(iex4_l2 & ~l3) |
(iex4_l1 & ~l3 & ~l2) |
(iex4_l0 & ~l3 & ~l2 & ~l1)) ;
//-------------------------------------------------------------------
assign riti0_p1 =
((riti0_l3) |
(riti0_l2 & ~l3) |
(riti0_l1 & ~l3 & ~l2) |
(riti0_l0 & ~l3 & ~l2 & ~l1)) ;
//-------------------------------------------------------------------
assign iex5_p1 =
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