isr.v

8051的Verilog实现

      end  
   end 

   //------------------------------------------------------------------
   // Interrupt Enable register 2
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : ien2_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      ien2 <= IEN0_RV ; 
      end
   else
      begin
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Special function register write
      //--------------------------------
      if (sfrwe & sfraddr == IEN2_ID)
         begin
         ien2 <= sfrdatai ; 
         end 
      end  
   end 

   //------------------------------------------------------------------
   // Interrupt Priority register 0
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : ip0_write_proc
   //------------------------------------------------------------------
   if (wdts)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      ip0 <= IP0_RW ; //set wdts flag (ip0(6))
      end
   else
      begin
      if (rst)
         begin
         ip0 <= IP0_RV ; 
         end
      else
         begin
         //-----------------------------------
         // Synchronous write
         //-----------------------------------
         // Special function register write
         //--------------------------------
         if (sfrwe & sfraddr == IP0_ID)
            begin
            ip0 <= sfrdatai ; 
            end 
         end 
      end  
   end 

   //------------------------------------------------------------------
   // Interrupt Priority register 1
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : ip1_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      ip1 <= IP1_RV ; 
      end
   else
      begin
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Special function register write
      //--------------------------------
      if (sfrwe & sfraddr == IP1_ID)
         begin
         ip1 <= sfrdatai ; 
         end 
      end  
   end 

   //------------------------------------------------------------------
   // Interrupt Request Control register
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : ircon_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      ircon <= IRCON_RV ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Special function register write
      //--------------------------------
      begin
      if (sfrwe & sfraddr == IRCON_ID)
         begin
         ircon <= sfrdatai ; 
         end
      else
         begin
         ircon[7] <= ircon[7] |  
                     (
                        (exf2 | exf2_ff) & ien1[7]
                     );
         ircon[6] <= ircon[6] | tf2 | tf2_ff;
         ircon[0] <= ircon[0] | iadc;
         if (intack)
            begin
            case (int_vect)
            VECT_EX6 : //iex6
               begin
               ircon[5] <= 1'b0 ; 
               end
            
            VECT_EX5 : //iex5
               begin
               ircon[4] <= 1'b0 ; 
               end
            
            VECT_EX4 : //iex4
               begin
               ircon[3] <= 1'b0 ; 
               end
            
            VECT_EX3 : //iex3
               begin
               ircon[2] <= 1'b0 ; 
               end
            
            VECT_EX2 : //iex2
               begin
               ircon[1] <= 1'b0 ; 
               end
            
            endcase 
            end
         else
            begin
            ircon[5:1] <= ({iex6, iex5, iex4, iex3, iex2}) |
               ircon[5:1] ; 
            end 
         end 
      end  
   end 

   //------------------------------------------------------------------
   // timer 2 overflow flip-flop
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : exf2_tf2_ff_proc
   //------------------------------------------------------------------
   //-----------------------------------
   // Synchronous reset
   //-----------------------------------
   if (rst)
      begin
      exf2_ff <= 1'b0;
      tf2_ff  <= 1'b0;
      end
   else
   //-----------------------------------
   // Synchronous write
   //-----------------------------------
      begin
      if (exf2)
         begin
         exf2_ff <= 1'b1;
         end
      else if (cycle == 1)
         begin
         exf2_ff <= 1'b0;
         end
      
      if (tf2)
         begin
         tf2_ff <= 1'b1;
         end
      else if (cycle == 1)
         begin
         tf2_ff <= 1'b0;
         end
      end
   end

   //------------------------------------------------------------------
   // External interrupt edge detect F/F
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : last_state_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      int2_p2 <= 1'b0 ; 
      int3_p2 <= 1'b0 ; 
      int4_p2 <= 1'b1 ; 
      int5_p2 <= 1'b1 ; 
      int6_p2 <= 1'b1 ; 
      
      int2_p0 <= 1'b0;
      int3_p0 <= 1'b0;
      int4_p0 <= 1'b1;
      int5_p0 <= 1'b1;
      int6_p0 <= 1'b1;
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      begin
      int2_p0 <= int2;
      int3_p0 <= int3;
      int4_p0 <= int4;
      int5_p0 <= int5;
      int6_p0 <= int6;

      int2_p2 <= int2_p0;
      int3_p2 <= int3_p1;
      int4_p2 <= int4_p1;
      int5_p2 <= int5_p1;
      int6_p2 <= int6_p1;
      end  
   end 
   
   //------------------------------------------------------------------
   assign int3_p1 = (ccen10) ? com0 : int3_p0 ; 
   
   //------------------------------------------------------------------
   assign int4_p1 = (ccen32) ? com1 : int4_p0 ; 
   
   //------------------------------------------------------------------
   assign int5_p1 = (ccen54) ? com2 : int5_p0 ; 
   
   //------------------------------------------------------------------
   assign int6_p1 = (ccen76) ? com3 : int6_p0 ; 

   //------------------------------------------------------------------
   // External interrupt edge detect
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : iex2_ff_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      iex2_ff <= 1'b0 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      begin
      if (cycle == 1)
         begin
         iex2_ff <= 1'b0 ; 
         end
      else if ((int2_p0 & !int2_p2 & i2fr) | // positive edge
              (!int2_p0 & int2_p2 & !i2fr))  // negative edge
         begin
         iex2_ff <= 1'b1 ; 
         end 
      end  
   end 
   
   //------------------------------------------------------------------
   // External interrupt edge detect
   //------------------------------------------------------------------
   
   assign iex2 = (i2fr) ? (int2_p0 & ~int2_p2) | iex2_ff // positive edge
      : (int2_p2 & ~int2_p0) | iex2_ff ;                 // negative edge

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : iex3_ff_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      iex3_ff <= 1'b0 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      begin
      if (~(ccen10_ff == ccen10) | cycle == 1)// compare <-> int3 switch
         begin
         iex3_ff <= 1'b0 ; 
         end
      else if ((int3_p1 & !int3_p2 & i3fr) | // positive edge
              (!int3_p1 & int3_p2 & !i3fr))  // negative edge
         begin
         iex3_ff <= 1'b1 ; 
         end 
      end  
   end 
   
   //------------------------------------------------------------------
   
   
   assign iex3 = (~(ccen10_ff == ccen10)) ? 1'b0 // compare <-> int3 switch
      : (i3fr) ? (int3_p1 & ~int3_p2) | iex3_ff :// positive edge
      (~int3_p1 & int3_p2) | iex3_ff ;           // negative edge

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : iex4_ff_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
         iex4_ff <= 1'b0 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      begin
      if (cycle == 1 | ~(ccen32_ff == ccen32)) // compare <-> int4 switch
         begin
         iex4_ff <= 1'b0 ; 
         end
      else if (int4_p1 & !int4_p2) // positive edge
         begin
         iex4_ff <= 1'b1 ; 
         end 
      end  
   end 
   
   //------------------------------------------------------------------
   assign iex4 = (~(ccen32_ff == ccen32)) ? 1'b0 // compare <-> int4 switch
      : (int4_p1 & ~int4_p2) | iex4_ff ;         // positive edge

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : iex5_ff_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin