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input com1; // compare output 1
input com2; // compare output 2
input com3; // compare output 3
input [7:0] ccenreg; //ccen reg.
// Serial 0 interrupt flags
input ri0; // Serial 0 receive flag
input ti0; // Serial 0 transmit flag
// Serial 1 interrupt flags
input ri1; // Serial 1 receive flag
input ti1; // Serial 1 transmit flag
// ADC interrupt flag
input iadc;
// External interrupt falling/rising edge flag
input i2fr; // Ext int 2 f/r edge flag
input i3fr; // Ext int 3 f/r edge flag
// wdt status flag
input wdts;
// Interrupt return signal
input intret;
// Interrupt acknowledge signal
input intack;
// Interrupt priority registers
output [1:0]intprior0;
wire [1:0]intprior0;
output [1:0]intprior1;
wire [1:0]intprior1;
// Interrupt mask
output eal; // Enable all interrupts
wire eal;
output eint0; // external interrupt 0 mask
wire eint0;
output eint1; // external interrupt 1 mask
wire eint1;
output etm0; // timer0 interrupt mask
wire etm0;
output etm1; // timer1 interrupt mask
wire etm1;
output etm2; // timer2 interrupt mask
wire etm2;
output esrl0; // serial0 interrupt mask
wire esrl0;
output esrl1; // serial1 interrupt mask
wire esrl1;
// Timer 0,1 acknowledge output
output t0ack; // Timer 0 int. acknowledge
reg t0ack;
output t1ack; // Timer 1 int. acknowledge
reg t1ack;
// External 0,1 acknowledge output
output int0ack; // External int0 acknowledge
reg int0ack;
output int1ack; // External int1 acknowledge
reg int1ack;
// Watchdog Timer control signals
output wdt; // WDT refresh flag
wire wdt;
// Interrupt Service location
output [4:0] intvect;
wire [4:0] intvect;
// Interrupt request signal
output intreq;
wire intreq;
// In Service register
output [3:0]isreg;
wire [3:0]isreg;
// Special function register interface
input [7:0] sfrdatai;
output [7:0] sfrdataisr;
wire [7:0] sfrdataisr;
input [6:0] sfraddr;
input sfrwe;
//------------------------------------------------------------------
// Interrupt Enable registers
reg [7:0] ien0;
reg [7:0] ien1;
reg [7:0] ien2;
// Interrupt Priority registers
reg [7:0] ip0;
reg [7:0] ip1;
// Interrupt Request Control register
reg [7:0] ircon;
// In Service register
reg [3:0] is_reg;
reg [3:0] is_nxt;
// External Interrupt flags
wire iex2; // int2 edge detect comb. output
wire iex3; // int3 edge detect comb. output
wire iex4; // int4 edge detect comb. output
wire iex5; // int5 edge detect comb. output
wire iex6; // int6 edge detect comb. output
// External Interrupt flip-flops
reg tf2_ff; // timer 2 overflow interrupt ff
reg exf2_ff; // timer 2 external interrupt ff
reg int2_p2; // last state int2 F/F
reg int3_p2; // last state int3 F/F
reg int4_p2; // last state int4 F/F
reg int5_p2; // last state int5 F/F
reg int6_p2; // last state int6 F/F
wire int3_p1; // current state int3
wire int4_p1; // current state int4
wire int5_p1; // current state int5
wire int6_p1; // current state int6
reg int2_p0; // current state int2
reg int3_p0; // current state int3
reg int4_p0; // current state int4
reg int5_p0; // current state int5
reg int6_p0; // current state int6
reg iex2_ff; // iex flip-flop
reg iex3_ff; // iex flip-flop
reg iex4_ff; // iex flip-flop
reg iex5_ff; // iex flip-flop
reg iex6_ff; // iex flip-flop
// Interrupt levels
reg ie0_l3;
reg ie0_l2;
reg ie0_l1;
reg ie0_l0;
reg riti1_l3;
reg riti1_l2;
reg riti1_l1;
reg riti1_l0;
reg iadc_l3;
reg iadc_l2;
reg iadc_l1;
reg iadc_l0;
reg tf0_l3;
reg tf0_l2;
reg tf0_l1;
reg tf0_l0;
reg iex2_l3;
reg iex2_l2;
reg iex2_l1;
reg iex2_l0;
reg ie1_l3;
reg ie1_l2;
reg ie1_l1;
reg ie1_l0;
reg iex3_l3;
reg iex3_l2;
reg iex3_l1;
reg iex3_l0;
reg tf1_l3;
reg tf1_l2;
reg tf1_l1;
reg tf1_l0;
reg iex4_l3;
reg iex4_l2;
reg iex4_l1;
reg iex4_l0;
reg riti0_l3;
reg riti0_l2;
reg riti0_l1;
reg riti0_l0;
reg iex5_l3;
reg iex5_l2;
reg iex5_l1;
reg iex5_l0;
reg tfexf2_l3;
reg tfexf2_l2;
reg tfexf2_l1;
reg tfexf2_l0;
reg iex6_l3;
reg iex6_l2;
reg iex6_l1;
reg iex6_l0;
wire l3;
wire l2;
wire l1;
wire l0;
reg l3_reg;
reg l2_reg;
reg l1_reg;
// Interrupt enable
reg ie0_en;
reg riti1_en;
reg iadc_en;
reg tf0_en;
reg iex2_en;
reg ie1_en;
reg iex3_en;
reg tf1_en;
reg iex4_en;
reg riti0_en;
reg iex5_en;
reg tfexf2_en;
reg iex6_en;
// Interrupt vector
wire ie0_p1;
wire riti1_p1;
wire iadc_p1;
wire tf0_p1;
wire iex2_p1;
wire ie1_p1;
wire iex3_p1;
wire tf1_p1;
wire iex4_p1;
wire riti0_p1;
wire iex5_p1;
wire tfexf2_p1;
wire iex6_p1;
// Compare Capture Enable register
wire ccen76;
wire ccen54;
wire ccen32;
wire ccen10;
reg ccen76_ff;
reg ccen54_ff;
reg ccen32_ff;
reg ccen10_ff;
// Combinational Interrupt Service location
reg [4:0] vect;
// Registered Interrupt Service location
reg [4:0] int_vect;
//------------------------------------------------------------------
// Watchdog Timer control signals
//------------------------------------------------------------------
assign wdt = ien0[6] ; // WDT refresh flag
//------------------------------------------------------------------
// In Service register
//------------------------------------------------------------------
assign isreg = is_reg;
//------------------------------------------------------------------
// Interrupt Priority registers
//------------------------------------------------------------------
assign intprior0 = {ip0[2], ip0[0]};
//------------------------------------------------------------------
// Interrupt Priority registers
//------------------------------------------------------------------
assign intprior1 = {ip1[2], ip1[0]};
//------------------------------------------------------------------
// All interrupts enable register
//------------------------------------------------------------------
assign eal = ien0[7];
//------------------------------------------------------------------
// INT0 enable register
//------------------------------------------------------------------
assign eint0 = ien0[0];
//------------------------------------------------------------------
// INT1 enable register
//------------------------------------------------------------------
assign eint1 = ien0[2];
//------------------------------------------------------------------
// timer0 enable register
//------------------------------------------------------------------
assign etm0 = ien0[1];
//------------------------------------------------------------------
// timer1 enable register
//------------------------------------------------------------------
assign etm1 = ien0[3];
//------------------------------------------------------------------
// timer2 enable register
//------------------------------------------------------------------
assign etm2 = ien0[5];
//------------------------------------------------------------------
// serial0 enable register
//------------------------------------------------------------------
assign esrl0 = ien0[4];
//------------------------------------------------------------------
// serial1 enable register
//------------------------------------------------------------------
assign esrl1 = ien2[0];
//------------------------------------------------------------------
// Interrupt Enable register 0
//------------------------------------------------------------------
always @(posedge clk)
begin : ien0_write_proc
//------------------------------------------------------------------
if (rst)
//-----------------------------------
// Synchronous reset
//-----------------------------------
begin
ien0 <= IEN0_RV ;
end
else
begin
if (sfrwe & sfraddr == IEN0_ID)
begin
ien0 <= sfrdatai ;
end
else
begin
//-----------------------------------
// Synchronous write
//-----------------------------------
// Special function register write
//--------------------------------
if (codefetche | debugfetche)
begin
ien0[6] <= 1'b0 ;
end
end
end
end
//------------------------------------------------------------------
// Interrupt Enable register 1
//------------------------------------------------------------------
always @(posedge clk)
begin : ien1_write_proc
//------------------------------------------------------------------
if (rst)
//-----------------------------------
// Synchronous reset
//-----------------------------------
begin
ien1 <= IEN1_RV ;
end
else
begin
//-----------------------------------
// Synchronous write
//-----------------------------------
// Special function register write
//--------------------------------
if (sfrwe & sfraddr == IEN1_ID)
begin
ien1[7] <= sfrdatai[7] ;
ien1[6] <= 1'b0 ;
ien1[5:0] <= sfrdatai[5:0] ;
end
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