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counter_st[2] |
counter_st[1]
)
begin
counter_nxt = counter_st - 2'b10 ;
end
else
begin
counter_nxt = counter_st - 1'b1 ;
end
end
default :
begin
if (md3[6])
begin
counter_nxt = counter_st - 1'b1 ;
end
else
begin
counter_nxt = counter_st - 2'b10 ;
end
end
endcase
end
2'b01 : //load
begin
counter_nxt = arcon[4:0] ;
end
default : // reset
begin
counter_nxt = 5'b00000 ;
end
endcase
end
//------------------------------------------------------------------
always @(posedge clk)
begin : counter_sync_proc
//------------------------------------------------------------------
if (rst)
//-----------------------------------
// Synchronous reset
//-----------------------------------
begin
counter_st <= 5'b00000 ;
end
else
begin
//-----------------------------------
// Synchronous write
//-----------------------------------
counter_st <= counter_nxt ;
end
end
//------------------------------------------------------------------
// adder
//------------------------------------------------------------------
always @(md0 or md1 or md2 or md3 or md4 or md5 or mdu_op or
norm_reg)
begin : sum1_comb_proc
//------------------------------------------------------------------
reg [17:0] arg_a;
reg [17:0] arg_b;
//-------------------------------
// arg_a --
//-------------------------------
case (mdu_op)
MDU_DIV16 :
begin
arg_a = {norm_reg, md1[7], 1'b1};
end
MDU_DIV32 :
begin
arg_a = {norm_reg, md3[7], 1'b1};
end
default :
begin
arg_a = {1'b0, md3, md2, 1'b0};
end
endcase
//-------------------------------
// arg_b --
//-------------------------------
case (mdu_op)
MDU_MUL :
begin
if (md0[0])
begin
arg_b = {1'b0, md5, md4, 1'b0};
end
else
begin
arg_b = {18{1'b0}};
end
end
default :
begin
arg_b = {1'b0, ~md5, ~md4, 1'b1};
end
endcase
sum1 = arg_a + arg_b ;
end
//------------------------------------------------------------------
always @(md0 or md1 or md3 or md4 or md5 or mdu_op or norm_reg or
sum1)
begin : sum_comb_proc
//------------------------------------------------------------------
reg [17:0] arg_c;
reg [17:0] arg_d;
//-------------------------------
// arg_c --
//-------------------------------
case (mdu_op)
MDU_DIV16 :
begin
if (sum1[17]) //CY=1
begin
arg_c = {sum1[16:1], md1[6], 1'b1};
end
else
begin
arg_c = {norm_reg [14:0], md1[7:6], 1'b1};
end
end
MDU_DIV32 :
begin
if (sum1[17]) //CY=1
begin
arg_c = {sum1[16:1], md3[6], 1'b1};
end
else
begin
arg_c = {norm_reg [14:0], md3[7:6], 1'b1};
end
end
default :
begin
arg_c = {1'b0, sum1[17:2], 1'b0};
end
endcase
//-------------------------------
// arg_d --
//-------------------------------
case (mdu_op)
MDU_MUL :
begin
if (md0[1])
begin
arg_d = {1'b0, md5, md4, 1'b0};
end
else
begin
arg_d = {18{1'b0}};
end
end
default :
begin
arg_d = {1'b0, ~md5, ~md4, 1'b1};
end
endcase
sum = arg_c + arg_d ;
end
//------------------------------------------------------------------
// load mdx FSM
//------------------------------------------------------------------
always @(lmdx_reg or sfrwe or sfraddr or opend or sfroe)
begin : lmdx_comb_proc
//------------------------------------------------------------------
case (lmdx_reg)
ST0 :
begin
mdu_op = MDU_NOP ;
setmdef = 1'b0 ;
if (sfrwe)
begin
case (sfraddr)
MD0_ID :
begin
lmdx_nxt = ST1 ;
end
ARCON_ID :
begin
lmdx_nxt = ST7 ;
end
default :
begin
lmdx_nxt = ST0 ;
end
endcase
end
else
begin
lmdx_nxt = ST0 ;
end
end
ST1 :
begin
mdu_op = MDU_RST ;
setmdef = 1'b0 ;
if (sfrwe)
begin
case (sfraddr)
MD0_ID :
begin
lmdx_nxt = ST13 ;
end
MD1_ID :
begin
lmdx_nxt = ST2 ;
end
MD4_ID :
begin
lmdx_nxt = ST10 ;
end
ARCON_ID :
begin
lmdx_nxt = ST7 ;
end
default :
begin
lmdx_nxt = ST1 ;
end
endcase
end
else
begin
lmdx_nxt = ST1 ;
end
end
ST2 :
begin
mdu_op = MDU_NOP ;
setmdef = 1'b0 ;
if (sfrwe)
begin
case (sfraddr)
MD0_ID :
begin
lmdx_nxt = ST13 ;
end
MD2_ID :
begin
lmdx_nxt = ST3 ;
end
MD4_ID :
begin
lmdx_nxt = ST8 ;
end
ARCON_ID :
begin
lmdx_nxt = ST7 ;
end
default :
begin
lmdx_nxt = ST2 ;
end
endcase
end
else
begin
lmdx_nxt = ST2 ;
end
end
ST3 :
begin
mdu_op = MDU_NOP ;
setmdef = 1'b0 ;
if (sfrwe)
begin
case (sfraddr)
MD0_ID :
begin
lmdx_nxt = ST13 ;
end
MD3_ID :
begin
lmdx_nxt = ST4 ;
end
ARCON_ID :
begin
lmdx_nxt = ST7 ;
end
default :
begin
lmdx_nxt = ST3 ;
end
endcase
end
else
begin
lmdx_nxt = ST3 ;
end
end
ST4 :
begin
mdu_op = MDU_NOP ;
setmdef = 1'b0 ;
if (sfrwe)
begin
case (sfraddr)
MD0_ID :
begin
lmdx_nxt = ST13 ;
end
MD4_ID :
begin
lmdx_nxt = ST5 ;
end
ARCON_ID :
begin
lmdx_nxt = ST7 ;
end
default :
begin
lmdx_nxt = ST4 ;
end
endcase
end
else
begin
lmdx_nxt = ST4 ;
end
end
ST5 :
begin
mdu_op = MDU_NOP ;
setmdef = 1'b0 ;
if (sfrwe)
begin
case (sfraddr)
MD0_ID :
begin
lmdx_nxt = ST13 ;
end
MD5_ID :
begin
lmdx_nxt = ST6 ;
end
ARCON_ID :
begin
lmdx_nxt = ST7 ;
end
default :
begin
lmdx_nxt = ST5 ;
end
endcase
end
else
begin
lmdx_nxt = ST5 ;
end
end
ST6 :
begin
mdu_op = MDU_DIV32 ;
setmdef = 1'b0 ;
if (sfrwe)
begin
case (sfraddr)
MD0_ID :
begin
lmdx_nxt = ST13 ;
end
MD1_ID, MD2_ID, MD3_ID,
MD4_ID, MD5_ID :
begin
lmdx_nxt = ST14 ;
end
default :
begin
lmdx_nxt = ST6 ;
end
endcase
end
else
begin
if (opend & sfraddr == MD5_ID & sfroe)
begin
lmdx_nxt = ST0 ;
end
else
begin
lmdx_nxt = ST6 ;
end
end
end
ST7 :
begin
mdu_op = MDU_SHIFT ;
setmdef = 1'b0 ;
if (sfrwe)
begin
case (sfraddr)
MD0_ID :
begin
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