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counter_st[2] | counter_st[1])
begin
md1 <= {md1[5:0], md0[7:6]} ;
end
else
begin
md1 <= {md1[6:0], md0[7]} ;
end
end
SHR :
begin
if (counter_st[4] | counter_st[3] |
counter_st[2] | counter_st[1])
begin
md1 <= {md2[1:0], md1[7:2]} ;
end
else
begin
md1 <= {md2[0], md1[7:1]} ;
end
end
NORM :
begin
if (md3[6])
begin
md1 <= {md1[6:0], md0[7]} ;
end
else
begin
md1 <= {md1[5:0], md0[7:6]} ;
end
end
DIV32, DIV16, LDRES :
begin
md1 <= {md1[5:0], md0[7:6]} ;
end
MUL :
begin
md1 <= {sum[1], sum1[1], md1[7:2]} ;
end
endcase
end
end
end
//------------------------------------------------------------------
// SFR md2 register write
//------------------------------------------------------------------
always @(posedge clk)
begin : md2_write_proc
//------------------------------------------------------------------
if (rst)
//-----------------------------------
// Synchronous reset
//-----------------------------------
begin
md2 <= MD2_RV ;
end
else
//-----------------------------------
// Synchronous write
//-----------------------------------
// Special function register write
//--------------------------------
begin
if (sfrwe & sfraddr == MD2_ID)
begin
md2 <= sfrdatai ;
end
else
begin
case (md30_sel)
SHL :
begin
if (counter_st[4] | counter_st[3] |
counter_st[2] | counter_st[1])
begin
md2 <= {md2[5:0], md1[7:6]} ;
end
else
begin
md2 <= {md2[6:0], md1[7]} ;
end
end
SHR :
begin
if (counter_st[4] | counter_st[3] |
counter_st[2] | counter_st[1])
begin
md2 <= {md3[1:0], md2[7:2]} ;
end
else
begin
md2 <= {md3[0], md2[7:1]} ;
end
end
NORM :
begin
if (md3[6])
begin
md2 <= {md2[6:0], md1[7]} ;
end
else
begin
md2 <= {md2[5:0], md1[7:6]} ;
end
end
DIV32, LDRES :
begin
md2 <= {md2[5:0], md1[7:6]} ;
end
MUL :
begin
md2 <= sum[9:2] ;
end
MD32RST :
begin
md2 <= 8'b00000000 ;
end
endcase
end
end
end
//------------------------------------------------------------------
// SFR md3 register write
//------------------------------------------------------------------
always @(posedge clk)
begin : md3_write_proc
//------------------------------------------------------------------
if (rst)
//-----------------------------------
// Synchronous reset
//-----------------------------------
begin
md3 <= MD3_RV ;
end
else
//-----------------------------------
// Synchronous write
//-----------------------------------
// Special function register write
//--------------------------------
begin
if (sfrwe & sfraddr == MD3_ID)
begin
md3 <= sfrdatai ;
end
else
begin
case (md30_sel)
SHL :
begin
if (counter_st[4] | counter_st[3] |
counter_st[2] | counter_st[1])
begin
md3 <= {md3[5:0], md2[7:6]} ;
end
else
begin
md3 <= {md3[6:0], md2[7]} ;
end
end
SHR :
begin
if (counter_st[4] | counter_st[3] |
counter_st[2] | counter_st[1])
begin
md3 <= {2'b00, md3[7:2]} ;
end
else
begin
md3 <= {1'b0, md3[7:1]} ;
end
end
NORM :
begin
if (md3[6])
begin
md3 <= {md3[6:0], md2[7]} ;
end
else
begin
md3 <= {md3[5:0], md2[7:6]} ;
end
end
DIV32, LDRES :
begin
md3 <= {md3[5:0], md2[7:6]} ;
end
MUL :
begin
md3 <= sum[17:10] ;
end
MD32RST :
begin
md3 <= 8'b00000000 ;
end
endcase
end
end
end
//------------------------------------------------------------------
// SFR md4 register write
//------------------------------------------------------------------
always @(posedge clk)
begin : md4_write_proc
//------------------------------------------------------------------
if (rst)
//-----------------------------------
// Synchronous reset
//-----------------------------------
begin
md4 <= MD4_RV ;
end
else
//-----------------------------------
// Synchronous write
//-----------------------------------
// Special function register write
//--------------------------------
begin
if (sfrwe & sfraddr == MD4_ID)
begin
md4 <= sfrdatai ;
end
else
begin
case (md30_sel)
LDRES :
begin
case (mdu_op)
MDU_DIV32 :
begin
if (sum[17])
begin
md4 <= sum[8:1] ;
end
else
begin
if (sum1[17])
begin
md4 <= {sum1[7:1], md3[6]} ;
end
else
begin
md4 <= {norm_reg [5:0], md3[7:6]} ;
end
end
end
default : // MDU_DIV16
begin
if (sum[17])
begin
md4 <= sum[8:1] ;
end
else
begin
if (sum1[17])
begin
md4 <= {sum1[7:1], md1[6]} ;
end
else
begin
md4 <= {norm_reg [5:0], md1[7:6]} ;
end
end
end
endcase
end
endcase
end
end
end
//------------------------------------------------------------------
// SFR md5 register write
//------------------------------------------------------------------
always @(posedge clk)
begin : md5_write_proc
//------------------------------------------------------------------
if (rst)
//-----------------------------------
// Synchronous reset
//-----------------------------------
begin
md5 <= MD5_RV ;
end
else
//-----------------------------------
// Synchronous write
//-----------------------------------
// Special function register write
//--------------------------------
begin
if (sfrwe & sfraddr == MD5_ID)
begin
md5 <= sfrdatai ;
end
else
begin
case (md30_sel)
LDRES :
begin
if (sum[17])
begin
md5 <= sum[16:9] ;
end
else
begin
if (sum1[17])
begin
md5 <= sum1[15:8] ;
end
else
begin
md5 <= norm_reg[13:6] ;
end
end
end
endcase
end
end
end
//------------------------------------------------------------------
// norm_reg register
//------------------------------------------------------------------
always @(posedge clk)
begin : norm_reg_write_proc
//------------------------------------------------------------------
if (rst)
//-----------------------------------
// Synchronous reset
//-----------------------------------
begin
norm_reg <= 16'b0000000000000000 ;
end
else
//-----------------------------------
// Synchronous write
//-----------------------------------
begin
case (md30_sel)
DIV32 :
begin
if (sum[17])
begin
norm_reg <= sum[16:1] ;
end
else
begin
if (sum1[17])
begin
norm_reg <= {sum1[15:1], md3[6]} ;
end
else
begin
norm_reg <= {norm_reg[13:0], md3[7:6]} ;
end
end
end
DIV16 :
begin
if (sum[17])
begin
norm_reg <= sum[16:1] ;
end
else
begin
if (sum1[17])
begin
norm_reg <= {sum1[15:1], md1[6]} ;
end
else
begin
norm_reg <= {norm_reg[13:0], md1[7:6]} ;
end
end
end
default :
begin
norm_reg <= 16'b0000000000000000 ;
end
endcase
end
end
//------------------------------------------------------------------
// counter
//------------------------------------------------------------------
always @(counter_sel or counter_st or arcon or md3 or md30_sel)
begin : counter_comb_proc
//------------------------------------------------------------------
case (counter_sel)
2'b11 : //dec
begin
case (md30_sel)
DIV16, DIV32, MUL :
begin
counter_nxt = counter_st - 2'b10 ;
end
SHR :
begin
if (
counter_st[4] |
counter_st[3] |
counter_st[2] |
counter_st[1]
)
begin
counter_nxt = counter_st - 2'b10 ;
end
else
begin
counter_nxt = counter_st - 1'b1 ;
end
end
SHL :
begin
if (
counter_st[4] |
counter_st[3] |
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