r80515.v

8051的Verilog实现

      .sfraddr       (ramsfraddr[6:0]),
      .sfrwe         (int_sfrwe)
      ); 
   
   //---------------------------------------------------------------
   // Multiplication Division Unit
   //---------------------------------------------------------------
   MDU U_MDU
      (
      .clk           (clkper),
      .rst           (rst),
      .sfrdatai      (sfrdataout),
      .sfrdatamdu    (sfrdatamdu),
      .sfraddr       (ramsfraddr[6:0]),
      .sfrwe         (int_sfrwe),
      .sfroe         (int_sfroe)
      ); 
   
   //---------------------------------------------------------------
   // External Memory Control Unit
   //---------------------------------------------------------------
   MEMORY_CONTROL #(ADDR_HIGH_P2_SEL) U_MEMCTRL
      (
      .clk           (clkcpu),
      .rst           (rst),
      .mempsackint   (mempsackint),
      .memackint     (memackint),
      .memack        (memack),
      .mempsack      (mempsack),
      .instr         (instr),
      .cycle         (cycle),
      .codefetche    (codefetche),
      .debugfetche   (debugfetche),
      .datafetche    (datafetche),
      .accreg        (accreg),
      .bitvalue      (bitvalue),
      .cdjump        (cdjump),
      .cyflag        (cyflag),
      .stretch       (stretch),
      .psstretch     (psstretch),
      .pmw           (pmw),
      .intreq        (intreq),
      .intcall       (intcall),
      .intvect       (intvect),
      .p2reg         (int_port2o),
      .ramdatai      (ramdatai),
      .mempsrdrst    (mempsrdrst),
      .a5instr       (a5instr),
      .debugreq      (debugreq),
      .debugprog     (debugprog),
      .flush         (flush_int),
      .mem2acc       (mem2acc),
      .pclreg        (pclreg),
      .pchreg        (pchreg),
      .ram2memaddr   (ram2memaddr),
      .memdatai      (memdatai),
      .memdatao      (memdatao),
      .memaddr       (memaddr),
      .mempswr       (mempswr),
      .mempsrd       (memps_rd),
      .memwr         (memwr),
      .memrd         (memrd),
      .sfrdatai      (sfrdataout),
      .sfrdatamcu    (sfrdatamcu),
      .sfraddr       (ramsfraddr[6:0]),
      .sfrwe         (int_sfrwe)
      ); 

   //---------------------------------------------------------------
   // Poower Management Unit
   //---------------------------------------------------------------
   OCI U_OCI
      (
      .clk           (clkcpu),
      .rst           (rst),
      .cycle         (cycle),
      .nrcycles      (nrcycles),
      .codefetche    (codefetche),
      .datafetche    (datafetche),
      .debugfetche   (debugfetche),
      .mempsackint   (mempsackint),
      .flush         (flush_int),
      .memdatai      (memdatai),
      .debugreq      (debugreq),
      .debugstep     (debugstep),
      .debugstepff   (debugstepff),
      .debugack      (debug_ack),
      .a5instr       (a5instr),
      .fetch         (fetch)
      );

   //---------------------------------------------------------------
   // Poower Management Unit
   //---------------------------------------------------------------
   PMU U_PMU
      (
      .clk           (clk),
      .rst           (rst),
      .rsto          (rst),
      .clkcpu        (clkcpuo),
      .clkper        (clkpero),
      .pmuintreq     (pmuintreq),
      .mempsrdrst    (mempsrdrst),
      .stoppmu       (stoppmu),
      .sfrdatai      (sfrdataout),
      .sfraddr       (ramsfraddr[6:0]),
      .sfrwe         (int_sfrwe)
      );
      
   //---------------------------------------------------------------
   // Reset Control
   //---------------------------------------------------------------
   RSTCTRL U_RSTCTRL 
      ( 
      .clk           (clk),       
      .rst           (rst),       
      .reset         (reset),     
      .wdts          (wdts),      
      .intreq        (intreq),    
      .int0          (int0),      
      .int1          (int1),      
      .it0           (it0),       
      .it1           (it1),       
      .isreg         (isreg),     
      .intprior0     (intprior0), 
      .intprior1     (intprior1), 
      .eal           (eal),       
      .eint0         (eint0),     
      .eint1         (eint1),     
      .mempsrdrst    (mempsrdrst),
      .pmuintreq     (pmuintreq)
      );

   //---------------------------------------------------------------
   // Port registers unit
   //---------------------------------------------------------------
   PORTS U_PORTS
      (
      .clk           (clkper),
      .rst           (rst),
      .port0i        (port0i),
      .port1i        (port1i),
      .port2i        (port2i),
      .port3i        (port3i),
      .rmwinstr      (rmwinstr),
      .ccubus        (ccubus),
      .port0o        (port0o),
      .port1o        (port1o),
      .port2o        (int_port2o),
      .port3o        (port3o),
      .sfrdatai      (sfrdataout),
      .sfrdataports  (sfrdataports),
      .sfraddr       (ramsfraddr[6:0]),
      .sfrwe         (int_sfrwe),
      .pio0          (pio0),
      .pio1          (pio1),
      .pio2          (pio2),
      .pio3          (pio3),
      .port_t        (port_t),
      .port_r        (port_r),
      .port_sel      (port_sel),
      .port_o        (port_o),
      .debugreq      (debugreq)
      ); 
   
   //---------------------------------------------------------------
   // 256B Data Memory and Special Function Registers Control Unit
   //---------------------------------------------------------------
   RAM_SFR_CONTROL U_RAMSFRCTRL
      (
      .clk           (clkcpu),
      .rst           (rst),
      .mempsackint   (mempsackint),
      .instr         (instr),
      .cycle         (cycle),
      .codefetche    (codefetche),
      .debugfetche   (debugfetche),
      .intreq        (intreq),
      .regsbank      (regsbank),
      .accreg        (accreg),
      .aluresult     (aluresult),
      .pclreg        (pclreg),
      .pchreg        (pchreg),
      .memdatai      (memdatai),
      .ram2memaddr   (ram2memaddr),
      .ramsfrdata    (ramsfrdata),
      .ramsfraddr    (ramsfraddr),
      .ramdatai      (ramdatai),
      .ramdatao      (ramdataout),
      .ramwe         (ramwe),
      .ramoe         (ramoe),
      .sfrdataalu    (sfrdataalu),
      .sfrdataclk    (sfrdataclk),
      .sfrdataisr    (sfrdataisr),
      .sfrdatamdu    (sfrdatamdu),
      .sfrdatamcu    (sfrdatamcu),
      .sfrdataports  (sfrdataports),
      .sfrdataser0   (sfrdataser0),
      .sfrdataser1   (sfrdataser1),
      .sfrdatatim    (sfrdatatim),
      .sfrdatatim2   (sfrdatatim2),
      .sfrdatawdt    (sfrdatawdt),
      .sfrdataext    (sfrdatai),
      .sfrdatao      (sfrdataout),
      .sfrwe         (int_sfrwe),
      .sfroe         (int_sfroe)
      ); 
   
   //---------------------------------------------------------------
   // Serial Interface Unit 0
   //---------------------------------------------------------------
   SERIAL_0 U_SERIAL0
      (
      .clk           (clkper),
      .rst           (rst),
      .cycle         (cycle),
      .rxd0i         (rxd0i),
      .t1ov          (t1ov),
      .smod          (smod),
      .ri0           (ri0),
      .ti0           (ti0),
      .rxd0o         (rxd0o),
      .txd0          (txd0),
      .sfrdatai      (sfrdataout),
      .sfrdataser0   (sfrdataser0),
      .sfraddr       (ramsfraddr[6:0]),
      .sfrwe         (int_sfrwe)
      ); 
   
   //---------------------------------------------------------------
   // Serial Interface Unit 1
   //---------------------------------------------------------------
   SERIAL_1 U_SERIAL1
      (
      .clk           (clkper),
      .rst           (rst),
      .rxd1i         (rxd1i),
      .txd1          (txd1),
      .ri1           (ri1),
      .ti1           (ti1),
      .sfrdatai      (sfrdataout),
      .sfrdataser1   (sfrdataser1),
      .sfraddr       (ramsfraddr[6:0]),
      .sfrwe         (int_sfrwe)
      ); 
   
   //---------------------------------------------------------------
   // Timer/Counter 0 and 1
   //---------------------------------------------------------------
   TIMER_0_1 U_TIMER
      (
      .clk           (clkper),
      .rst           (rst),
      .cycle         (cycle),
      .t0            (t0),
      .t1            (t1),
      .t0ack         (t0ack),
      .t1ack         (t1ack),
      .int0          (int0),
      .int1          (int1),
      .int0ack       (int0ack),
      .int1ack       (int1ack),
      .tf0           (tf0),
      .tf1           (tf1),
      .ie0           (ie0),
      .ie1           (ie1),
      .it0           (it0),
      .it1           (it1),  
      // my control signal ///////////////
      .cnt0_mode     (cnt0_mode),
      .cnt1_mode     (cnt1_mode), 
      ////////////////////////////////////
      .t1ov          (t1ov),
      .sfrdatai      (sfrdataout),
      .sfrdatatim    (sfrdatatim),
      .sfraddr       (ramsfraddr[6:0]),
      .sfrwe         (int_sfrwe)
      ); 
   
   //---------------------------------------------------------------
   // Timer/Counter 2 and Capture/Compare Unit
   //---------------------------------------------------------------
   TIMER_2 U_TIMER2
      (
      .clk           (clkper),
      .rst           (rst),
      .t2            (t2),
      .t2ex          (t2ex),
      .cc0           (cc0),
      .cc1           (cc1),
      .cc2           (cc2),
      .cc3           (cc3),
      .com0          (com0),
      .com1          (com1),
      .com2          (com2),
      .com3          (com3),
      .ccenreg       (ccenreg),
      .i2fr          (i2fr),
      .i3fr          (i3fr),
      .tf2           (tf2),
      .exf2          (exf2), 
      // my control signal //////////
      .coca0_mode    (coca0_mode),
      .coca1_mode    (coca1_mode),
      .coca2_mode    (coca2_mode),
      .coca3_mode    (coca3_mode),  
      .cnt2_mode     (cnt2_mode),
      .rtm2_mode     (rtm2_mode),
      .ccubus        (ccubus), 
      ////////////////////////////////
      .sfrdatai      (sfrdataout),
      .sfrdatatim2   (sfrdatatim2),
      .sfraddr       (ramsfraddr[6:0]),
      .sfrwe         (int_sfrwe)
      ); 
   
   //---------------------------------------------------------------
   // Programmable Watchdog Timer
   //---------------------------------------------------------------
   WATCHDOG_TIMER U_WDT
      (
      .clk           (clkper),
      .rst           (rst),
      .wdt           (wdt),
      .swd           (swd),
      .wdts          (wdts),
      .sfrdatai      (sfrdataout),
      .sfrdatawdt    (sfrdatawdt),
      .sfraddr       (ramsfraddr[6:0]),
      .sfrwe         (int_sfrwe)
      ); 


endmodule //  module R80515

//*******************************************************************--