r80515.v

8051的Verilog实现

   wire     cyflag; 
   wire     [7:0] sfrdataalu; 
   
   //---------------------------------------------------------------
   // Clock Control Unit signals
   //---------------------------------------------------------------
   wire     smod;          // Baud rate Doubler
   wire     pmw;           // Program memory write
   wire     [2:0] stretch;
   wire     [2:0] psstretch;
   wire     [7:0] sfrdataclk;
   wire     mempsackint;   
   
   //---------------------------------------------------------------
   // Control Processor Unit signals
   //---------------------------------------------------------------
   wire     [7:0] instr; 
   wire     [3:0] cycle;   // Current machine cycle
   wire     [3:0] nrcycles;// Number of machine cycles
   wire     codefetche;    // Opcode fetch enable
   wire     datafetche;    // Data fetch enable
   wire     intack;        // Interrupt acknowledge flag
   wire     intret;        // Interrupt return flag
   wire     intcall;       // Interrupt call
   wire     storefetche;   // Store fetch enable
   wire     debugstepff;   // Debug step flip-flop
   
   //---------------------------------------------------------------
   // Interrupt Service Routine Unit signals
   //---------------------------------------------------------------
   wire     t0ack;         // Timer 0 int. acknowledge
   wire     t1ack;         // Timer 1 int. acknowledge 
   wire     int0ack;       // External int0 acknowledge
   wire     int1ack;       // External int1 acknowledge
   wire     wdt;           // WDT refresh flag
   wire     intreq;        // Interrupt request flag
   wire     [4:0] intvect;
   wire     [3:0] isreg;
   wire     [1:0] intprior0;
   wire     [1:0] intprior1;
   wire     [7:0] sfrdataisr; 
   
   //---------------------------------------------------------------
   // Multiplication Division Unit signals
   //---------------------------------------------------------------
   wire     [7:0] sfrdatamdu;
   wire     [7:0] int_port2o; 
   
   //---------------------------------------------------------------
   // Power Management Unit
   //---------------------------------------------------------------
   wire     rst;           // reset
   wire     mempsrdrst;    // memory read signal reset
   wire     stoppmu;       // stop mode

   //---------------------------------------------------------------
   // Port registers unit signals
   //---------------------------------------------------------------
   wire     [7:0] sfrdataports; 
   
   //---------------------------------------------------------------
   // Memory Control Unit signals
   //---------------------------------------------------------------
   wire     mem2acc;       // Memory to ACC write enable
   wire     [7:0] pclreg; 
   wire     [7:0] pchreg; 
   wire     [7:0] sfrdatamcu; 
   wire     ram2memaddr;   // RAM to MemAddr write enable
   wire     memps_rd;
   
   //---------------------------------------------------------------
   // 256B Data Memory and Special Function Registers Control Unit
   //---------------------------------------------------------------
   wire     [7:0] ramsfrdata; 
   wire     [7:0] sfrdataout; 
   wire     [7:0] ramsfraddr; 
   wire     [7:0] ramdataout; 
   
   //---------------------------------------------------------------
   // On-Chip Debug Support interface
   //---------------------------------------------------------------
   wire     flush_int;
   wire     a5instr;
   wire     debugfetche;
   wire     debug_ack;

   //---------------------------------------------------------------
   // Serial Interface Unit 0 signals
   //---------------------------------------------------------------
   wire     ri0;           // Serial 0 receive flag
   wire     ti0;           // Serial 0 transmit flag
   wire     [7:0] sfrdataser0; 
   
   //---------------------------------------------------------------
   // Serial Interface Unit 1 signals
   //---------------------------------------------------------------
   wire     ri1;           // Serial 1 receive flag
   wire     ti1;           // Serial 1 transmit flag
   wire     [7:0] sfrdataser1; 
   
   //---------------------------------------------------------------
   // Timer/Counter 0 and 1 signals
   //---------------------------------------------------------------
   wire     tf0;           // Timer 0 overflow flag
   wire     tf1;           // Timer 1 overflow flag
   wire     ie0;           // Interrupt 0 edge detect
   wire     ie1;           // Interrupt 1 edge detect
   wire     it0;           // Interrupt 0 edge/low sel.
   wire     it1;           // Interrupt 1 edge/low sel.
   wire     t1ov;          // Timer 1 overflow output
   wire     [7:0] sfrdatatim; 
   
   //---------------------------------------------------------------
   // Timer/Counter 2 and Capture/Compare Unit signals
   //---------------------------------------------------------------
   wire     com0;          // Compare 0 output
   wire     com1;          // Compare 1 output
   wire     com2;          // Compare 2 output
   wire     com3;          // Compare 3 output
   wire     i2fr; 
   wire     i3fr; 
   wire     tf2;           // Timer 2 overflow signal
   wire     exf2;          // Timer 2 external signal
   wire     [3:0] ccubus; 
   wire     [7:0] sfrdatatim2; 
   wire     [7:0] ccenreg; 
   
   //---------------------------------------------------------------
   // Programmable Watchdog Timer signals
   //---------------------------------------------------------------
   wire     wdts;             // WDT status flag
   wire     [7:0] sfrdatawdt; 

   wire     memackint; 
      
   wire     pmuintreq;     
   

   //------------------------------------------------------------------
   // Memory interface
   //------------------------------------------------------------------
   assign mempsrd = memps_rd;

   assign mempsacko = mempsackint;

   //------------------------------------------------------------------
   // Data file interface
   // Data bus output
   //------------------------------------------------------------------
   assign ramdatao = ramdataout ; 
   
   //------------------------------------------------------------------
   // Data file interface
   // Address bus output
   //------------------------------------------------------------------
   assign ramaddr = ramsfraddr ; 
   
   //------------------------------------------------------------------
   // External Special function register interface
   // Data bus output
   //------------------------------------------------------------------
   assign sfrdatao = sfrdataout ; 
   
   //------------------------------------------------------------------
   // External Special function register interface
   // Address bus output
   //------------------------------------------------------------------
   assign sfraddr = ramsfraddr[6:0] ; 
   
   //------------------------------------------------------------------
   // External Special function register interface
   // Write enable output
   //------------------------------------------------------------------
   assign sfrwe = int_sfrwe ; 
   
   //------------------------------------------------------------------
   // External Special function register interface
   // Output enable output
   //------------------------------------------------------------------
   assign sfroe = int_sfroe ; 
   
   //------------------------------------------------------------------
   // ADC interrupt flag
   //------------------------------------------------------------------
   assign iadc = 1'b0 ; 

   //------------------------------------------------------------------
   // Debug acknowledge
   //------------------------------------------------------------------
   assign debugack = debug_ack ;

   assign flush = flush_int ; 
 
   assign acc = accreg ;

   //------------------------------------------------------------------
   // Port 2 output
   //------------------------------------------------------------------
   assign port2o = int_port2o;
   
   //---------------------------------------------------------------
   // Aritmetic Logic Unit
   //---------------------------------------------------------------
   ALU U_ALU
      (
      .clk           (clkcpu),
      .rst           (rst),
      .mempsackint   (mempsackint),
      .instr         (instr),
      .cycle         (cycle),
      .memdatai      (memdatai),
      .mem2acc       (mem2acc),
      .ramsfrdata    (ramsfrdata),
      .accreg        (accreg),
      .aluresult     (aluresult),
      .regsbank      (regsbank),
      .bitvalue      (bitvalue),
      .cdjump        (cdjump),
      .cyflag        (cyflag),
      .sfrdatai      (sfrdataout),
      .sfrdataalu    (sfrdataalu),
      .sfraddr       (ramsfraddr[6:0]),
      .sfrwe         (int_sfrwe)
      ); 
      
   //---------------------------------------------------------------
   // Clock Control Unit
   //---------------------------------------------------------------
   CLOCK_CONTROL U_CLKCTRL
      (
      .clk           (clkper),
      .rst           (rst),
      .mempsrd       (memps_rd),
      .mempswr       (mempswr),
      .debugreq      (debugreq),
      .smod          (smod),
      .pmw           (pmw),
      .stretch       (stretch),
      .psstretch     (psstretch),
      .mempsackint   (mempsackint),
      .mempsack      (mempsack),
      .sfrdatai      (sfrdataout),
      .sfrdataclk    (sfrdataclk),
      .sfraddr       (ramsfraddr[6:0]),
      .sfrwe         (int_sfrwe)
      );
      
   //---------------------------------------------------------------
   // Control Processor Unit
   //---------------------------------------------------------------
   CONTROL_UNIT U_CPU
      (
      .clk           (clkcpu),
      .rst           (rst),
      .mempsackint   (mempsackint),
      .memackint     (memackint),   
      .intreq        (intreq),
      .stretch       (stretch),
      .stoppmu       (stoppmu),
      .debugreq      (debugreq),
      .debugack      (debugack),
      .debugstep     (debugstepff),
      .a5instr       (a5instr),
      .debugfetche   (debugfetche),
      .instr         (instr),
      .cycle         (cycle),
      .nrcycles      (nrcycles),
      .codefetche    (codefetche),
      .datafetche    (datafetche), 
      .rmwinstr      (rmwinstr),
      .intack        (intack),
      .intret        (intret),
      .intcall       (intcall),
      .memdatai      (memdatai),
      .sfrwe         (sfrwe)
      ); 
   
   //---------------------------------------------------------------
   // Interrupt Service Routine Unit
   //---------------------------------------------------------------
   ISR U_ISR
      (
      .clk           (clkper),
      .rst           (rst),
      .cycle         (cycle),
      .instr         (instr),
      .codefetche    (codefetche),
      .debugfetche   (debugfetche),
      .debugreq      (debugreq),
      .a5instr       (a5instr),
      .tf0           (tf0),
      .ie0           (ie0),
      .tf1           (tf1),
      .ie1           (ie1),
      .tf2           (tf2),
      .exf2          (exf2),
      .int2          (int2),
      .int3          (int3),
      .int4          (int4),
      .int5          (int5),
      .int6          (int6),
      .com0          (com0),
      .com1          (com1),
      .com2          (com2),
      .com3          (com3),
      .ccenreg       (ccenreg),
      .ri0           (ri0),
      .ti0           (ti0),
      .ri1           (ri1),
      .ti1           (ti1),
      .iadc          (iadc),
      .i2fr          (i2fr),
      .i3fr          (i3fr),
      .wdts          (wdts),
      .intret        (intret),
      .intack        (intack),
      .intprior0     (intprior0),
      .intprior1     (intprior1), 
      // my control signal///////////////////////////
      .eal           (eal),
      .eint0         (eint0),
      .eint1         (eint1),
      .etm0          (etm0),
      .etm1          (etm1),
      .etm2          (etm2),
      .esrl0         (esrl0),
      .esrl1         (esrl1), 
      ///////////////////////////////////////////////
      .t0ack         (t0ack),
      .t1ack         (t1ack),
      .int0ack       (int0ack),
      .int1ack       (int1ack),
      .wdt           (wdt),
      .intvect       (intvect),
      .intreq        (intreq),
      .isreg         (isreg),
      .sfrdatai      (sfrdataout),
      .sfrdataisr    (sfrdataisr),