clkctrl.v

8051的Verilog实现

   parameter[7:0] MOV_R6_A       = 8'b11111110; 
   parameter[7:0] MOV_R7_A       = 8'b11111111; 
   
   //-----------------------------------------------------------------
   // Interrupt reset values
   //-----------------------------------------------------------------
   parameter[4:0] VECT_RV        = 5'b00000; // Interrupt Vector reset value
   parameter[3:0] IS_REG_RV      = 4'b0000;  // In Service Register reset value

   //-----------------------------------------------------------------
   // Interrupt Vector locations
   //-----------------------------------------------------------------
   // external interrupt 0
   parameter[4:0] VECT_E0        = 5'b00000; 
   
   // timer 0 overflow
   parameter[4:0] VECT_TF0       = 5'b00001; 
   
   // external interrupt 1
   parameter[4:0] VECT_E1        = 5'b00010; 
   
   // timer 1 overflow
   parameter[4:0] VECT_TF1       = 5'b00011; 
   
   // serial channel 0
   parameter[4:0] VECT_SER0      = 5'b00100; 
   
   // timer 2 overflow/ext. reload
   parameter[4:0] VECT_TF2       = 5'b00101; 
   
   // A/D converter 
   parameter[4:0] VECT_ADC       = 5'b01000; 
   
   // external interrupt 2
   parameter[4:0] VECT_EX2       = 5'b01001; 
   
   // external interrupt 3
   parameter[4:0] VECT_EX3       = 5'b01010; 
   
   // external interrupt 4
   parameter[4:0] VECT_EX4       = 5'b01011; 
   
   // external interrupt 5
   parameter[4:0] VECT_EX5       = 5'b01100; 
   
   // external interrupt 6
   parameter[4:0] VECT_EX6       = 5'b01101; 
   
   // serial channel 1
   parameter[4:0] VECT_SER1      = 5'b10000; 

   //-----------------------------------------------------------------
   // Start address location
   //-----------------------------------------------------------------
   parameter[15:0] ADDR_RV       = 16'b0000000000000000; //


   //-----------------------------------------------------------------
   // RAM & SFR address reset value
   //-----------------------------------------------------------------
   parameter[7:0] RAM_SFR_ADDR_RV= 8'b00000000; //


   //-----------------------------------------------------------------
   // Data register reset value
   //-----------------------------------------------------------------
   parameter[7:0] DATAREG_RV     = 8'b00000000; //


   //-----------------------------------------------------------------
   // High ordered half of address during indirect addressing
   //-----------------------------------------------------------------
   parameter[7:0] ADDR_HIGH_RI   = 8'b00000000; //


   //-----------------------------------------------------------------
   // Watchdog Timer reset value
   //-----------------------------------------------------------------
   parameter[6:0] WDTH_RV        = 7'b0000000;  // High ordered WDT
   parameter[7:0] WDTL_RV        = 8'b00000000; // Low ordered WDT


   //-----------------------------------------------------------------
   // Watchdog Timer reset state
   //-----------------------------------------------------------------
   parameter[14:0] WDT_RS        = 15'b111111111111100; // X"7FFC"



//*******************************************************************--   
   //  Control signals inputs
   input       clk;     // Global clock input
   input       rst;     // Internal reset input

   //  Program memory read
   input       mempsrd;

   // Program memory write
   input       mempswr;

   //  Debug Request
   input       debugreq;
   
   //  Clock Control outputs
   output      smod;    // Baud rate Doubler
   wire        smod;
   output      pmw;     // Program memory write
   wire        pmw;
   output      [2:0] stretch; 
   wire        [2:0] stretch;
   output      [2:0] psstretch;
   wire        [2:0] psstretch;

   //  Program memory waitstates
   output      mempsackint;
   wire        mempsackint;
   input       mempsack;
   
   //  Special function register interface
   input       [7:0] sfrdatai; 
   output      [7:0] sfrdataclk; 
   wire        [7:0] sfrdataclk;
   input       [6:0] sfraddr; 
   input       sfrwe; 

   //------------------------------------------------------------------
   
   // Power Control register
   reg         [7:2] pcon; 
   
   // Clock Control register
   reg         [7:0] ckcon; 
   
   // Wait states counter
   reg         [2:0] waitcount;
   
   //------------------------------------------------------------------
   // Baud rate Doubler
   //------------------------------------------------------------------
   assign smod = pcon[7] ;

   //------------------------------------------------------------------
   // Program Memory Write flag
   //------------------------------------------------------------------
   assign pmw = pcon[4] ;
 
   //------------------------------------------------------------------
   // Data Memory cycle stretch control
   //------------------------------------------------------------------
   assign stretch = ckcon[2:0] ; 

   //------------------------------------------------------------------
   // Data Memory cycle stretch control
   //------------------------------------------------------------------
   assign psstretch = ckcon[6:4] ;

   //------------------------------------------------------------------
   // pcon register
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : pcon_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      pcon <= PCON_RV[7:2] ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Special function register write
      //--------------------------------
      begin
      if (sfrwe & sfraddr == PCON_ID)
         begin
         pcon <= sfrdatai[7:2] ; 
         end 
      end  
   end 

   //------------------------------------------------------------------
   // ckcon register
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : ckcon_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      ckcon <= CKCON_RV ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Special function register write
      //--------------------------------
      begin
      if (sfrwe & sfraddr == CKCON_ID)
         begin
         ckcon <= sfrdatai ; 
         end 
      end  
   end 

   //------------------------------------------------------------------
   // Wait states counter
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : waitcount_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      waitcount <= CKCON_RV[6:4];
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Current cycle count
      //--------------------------------
      begin
      if (mempsrd) // & (!debugreq)
         begin
         if (waitcount == 3'b000)
            begin
            if (mempsack)
              begin
              waitcount <= ckcon[6:4];
              end
            end
         else
            begin
            waitcount <= waitcount - 3'b001;
            end
         end
      else
         begin
         waitcount <= ckcon[6:4];
         end
      end
   end
      
   //------------------------------------------------------------------
   // Program memory acknowledge
   //------------------------------------------------------------------
   assign mempsackint = ((waitcount == 3'b000 | (!mempsrd &
                                                 !mempswr)) & 
                         (mempsack            | (!mempsrd &
                                                 !mempswr))) ? 1'b1 : 1'b0;
   
   //------------------------------------------------------------------
   // Special Function registers read
   //------------------------------------------------------------------
   assign sfrdataclk = (sfraddr == PCON_ID) ? {pcon, 2'b00} :
                       (sfraddr == CKCON_ID) ? ckcon :
                       "--------" ; 

endmodule  // module CLOCK_CONTROL

//*******************************************************************--