timer2.v

8051的Verilog实现

         com_int2 = 1'b0 ; 
         end 
      end
   
   default :
      begin
      com_int2 = 1'b0 ; 
      end
   
   endcase 
   
   case (ccen[7:6])
   2'b10 :
      begin
      if ((tl2 == ccl3) & (th2 == cch3))
         begin
         com_int3 = 1'b1 ; 
         end
      else
         begin
         com_int3 = 1'b0 ; 
         end 
      end
   
   default :
      begin
      com_int3 = 1'b0 ; 
      end
   
   endcase 
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : timer2_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      tl2 <= TL2_RV ; 
      th2 <= TH2_RV ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Timer 2 Reload
      //--------------------------------
      // Mode 0
      //--------------------------------
      begin
      if ((((t2con[4]) & !(t2con[3])) & th2_ov) |
         //--------------------------------
         // Mode 1
         //--------------------------------
         (((t2con[4]) & (t2con[3])) & t2ex_fall))
         begin
         tl2 <= crcl ; 
         th2 <= crch ; 
         end
      else
         //--------------------------------
         // Timer 2 Count
         //--------------------------------
         begin
         if (tl2_clk)
            begin
            tl2 <= tl2 + 1'b1 ; 
            end 
         
         if (th2_clk)
            begin
            th2 <= th2 + 1'b1 ; 
            end 
         
         end 
         
      //--------------------------------
      // Special function register write
      //--------------------------------
      if (sfrwe & sfraddr == TL2_ID)
         begin
         tl2 <= sfrdatai ; 
         end 
      
      if (sfrwe & sfraddr == TH2_ID)
         begin
         th2 <= sfrdatai ; 
         end 
      
      end  
   end 

   //------------------------------------------------------------------
   // Clock counter with overflow divided by 12 or 24
   // clk_ov12 is high active during single clk period
   // clk_ov24 is high active during single clk period
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : clk_count_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      clk_count <= 5'b00000 ; 
      clk_ov12 <= 1'b0 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Clock counter
      //--------------------------------
      begin
      if (clk_count == 5'b10111)
         begin
         clk_count <= 5'b00000 ; 
         end
      else
         begin
         clk_count <= clk_count + 1'b1 ; 
         end 
         
      //--------------------------------
      // Clock divided by 12
      //--------------------------------
      if (clk_count == 5'b01011)
         begin
         clk_ov12 <= 1'b1 ; 
         end
      else if (clk_count == 5'b10111)
         begin
         clk_ov12 <= 1'b1 ; 
         end
      else
         begin
         clk_ov12 <= 1'b0 ; 
         end 
      
      //--------------------------------
      // Clock divided by 24
      //--------------------------------
      if (clk_count == 5'b10111)
         begin
         clk_ov24 <= 1'b1 ; 
         end
      else
         begin
         clk_ov24 <= 1'b0 ; 
         end 
      
      end  
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : det_ff_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      t2_ff    <= 1'b0 ; 
      t2_ff0   <= 1'b0 ; 
      cc1_ff   <= 1'b0 ; 
      cc1_ff0  <= 1'b0 ; 
      cc2_ff   <= 1'b0 ; 
      cc2_ff0  <= 1'b0 ; 
      cc3_ff   <= 1'b0 ; 
      cc3_ff0  <= 1'b0 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // t2 input flip-flop
      //--------------------------------
      begin
      t2_ff0   <= t2 ; 
      cc1_ff0  <= cc1 ; 
      cc2_ff0  <= cc2 ; 
      cc3_ff0  <= cc3 ; 
      t2_ff    <= t2_ff0 ; 
      cc1_ff   <= cc1_ff0 ; 
      cc2_ff   <= cc2_ff0 ; 
      cc3_ff   <= cc3_ff0 ; 
      end  
   end 

   //------------------------------------------------------------------
   // Falling edge detection on the external input t2
   // t2_fall is high active during single clk period
   //------------------------------------------------------------------
   always @(t2_ff0 or t2_ff or cc1_ff0 or cc1_ff or cc2_ff0 or
      cc2_ff or cc3_ff0 or cc3_ff)
   begin : det_rise_fall_proc
   //------------------------------------------------------------------
   //--------------------------------
   // Falling edge detection
   //--------------------------------
   if (!t2_ff0 & t2_ff)
      begin
      t2_fall = 1'b1 ; 
      end
   else
      begin
      t2_fall = 1'b0 ; 
      end 
   //--------------------------------
   // Rising edge detection
   //--------------------------------
   if (cc1_ff0 & !cc1_ff)
      begin
      cc1_rise = 1'b1 ; 
      end
   else
      begin
      cc1_rise = 1'b0 ; 
      end 
   if (cc2_ff0 & !cc2_ff)
      begin
      cc2_rise = 1'b1 ; 
      end
   else
      begin
      cc2_rise = 1'b0 ; 
      end 
   if (cc3_ff0 & !cc3_ff)
      begin
      cc3_rise = 1'b1 ; 
      end
   else
      begin
      cc3_rise = 1'b0 ; 
      end 
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : cc0_ff_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      cc0_ff <= 1'b0 ; 
      cc0_ff0 <= 1'b0 ; 
      end
   else
      begin
      cc0_ff0 <= cc0 ; 
      cc0_ff <= cc0_ff0 ; 
      end  
   end 

   //------------------------------------------------------------------
   always @(cc0_ff0 or cc0_ff or t2con)
   begin : cc0_fall_rise_proc
   //------------------------------------------------------------------
   if (t2con[6])
      //--------------------------------
      // Rising edge detection
      //--------------------------------
      begin
      if (cc0_ff0 & !cc0_ff)
         begin
         cc0_fall_rise = 1'b1 ; 
         end
      else
         begin
         cc0_fall_rise = 1'b0 ; 
         end 
      end
   else
      //--------------------------------
      // Falling edge detection
      //--------------------------------
      begin
      if (!cc0_ff0 & cc0_ff)
         begin
         cc0_fall_rise = 1'b1 ; 
         end
      else
         begin
         cc0_fall_rise = 1'b0 ; 
         end 
      end 
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : t2ex_ff_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      t2ex_ff <= 1'b0 ; 
      t2ex_ff0 <= 1'b0 ; 
      end
   else
      //--------------------------------
      // t2ex trigger flip-flop
      //--------------------------------
      begin
      t2ex_ff0 <= t2ex ; 
      t2ex_ff <= t2ex_ff0 ; 
      end  
   end 

   //------------------------------------------------------------------
   // Falling edge detection on the external trigger t2ex
   // t2ex_fall is high active during single clk period
   //------------------------------------------------------------------
   always @(t2ex_ff0 or t2ex_ff)
   begin : t2ex_fall_proc
   //------------------------------------------------------------------
   //--------------------------------
   // Falling edge detection
   //--------------------------------
   if (!t2ex_ff0 & t2ex_ff)
      begin
      t2ex_fall = 1'b1 ; 
      end
   else
      begin
      t2ex_fall = 1'b0 ; 
      end 
   end 
   
   //------------------------------------------------------------------
   // Compare output signal
   //------------------------------------------------------------------
   assign com0 = com_int0 ; 
   assign com1 = com_int1 ; 
   assign com2 = com_int2 ; 
   assign com3 = com_int3 ; 
   
   //------------------------------------------------------------------
   // ISR control signals
   //------------------------------------------------------------------
   assign i2fr = t2con[5] ; 
   assign i3fr = t2con[6] ; 
   
   //------------------------------------------------------------------
   // CCU_bus output
   //------------------------------------------------------------------
   assign ccubus[0] = cc0_out_int ; 
   assign ccubus[1] = cc1_out_int ; 
   assign ccubus[2] = cc2_out_int ; 
   assign ccubus[3] = cc3_out_int ; 
   
   //------------------------------------------------------------------
   // Timer 2 high ordered byte clock
   // th2_clk is high active during single clk period
   //------------------------------------------------------------------
   assign th2_clk = tl2_ov ; 
   
   //------------------------------------------------------------------
   // Timer low 2 overflow
   // tl2_ov is high active during single clk period
   //------------------------------------------------------------------
   assign tl2_ov =
      (tl2[7:0] == 8'b11111111) ? tl2_clk :
      1'b0 ; 
   
   //------------------------------------------------------------------
   // Timer high 2 overflow
   // th0_ov is high active during single clk period
   //------------------------------------------------------------------
   assign th2_ov =
      (th2[7:0] == 8'b11111111) ? th2_clk :
      1'b0 ; 
   
   //------------------------------------------------------------------
   // Special Function registers read
   //------------------------------------------------------------------
   assign sfrdatatim2 =
      (sfraddr == TL2_ID) ? tl2 :
      (sfraddr == TH2_ID) ? th2 :
      (sfraddr == CRCL_ID) ? crcl :
      (sfraddr == CRCH_ID) ? crch :
      (sfraddr == T2CON_ID) ? t2con :
      (sfraddr == CCEN_ID) ? ccen :
      (sfraddr == CCL1_ID) ? ccl1 :
      (sfraddr == CCH1_ID) ? cch1 :
      (sfraddr == CCL2_ID) ? ccl2 :
      (sfraddr == CCH2_ID) ? cch2 :
      (sfraddr == CCL3_ID) ? ccl3 :
      (sfraddr == CCH3_ID) ? cch3 :
      "--------" ; 


endmodule  //  module TIMER_2

//*******************************************************************--