timer2.v

8051的Verilog实现

      .pout       (cc0_out_int),
      .sfrdatai   (sfrdatai[0]),
      .sfraddr    (sfraddr),
      .sfrwe      (sfrwe)
      ); 
   
   //---------------------------------------------------------------
   // Compare/Capture Bit Port 1 Control
   //---------------------------------------------------------------
   CCU_PORT CCU_PORT_1
      (
      .clk        (clk),
      .rst        (rst),
      .compare    (com_int1),
      .ov         (th2_ov),
      .cocahl     (ccen[3:2]),
      .t2cm       (t2con[2]),
      .pout       (cc1_out_int),
      .sfrdatai   (sfrdatai[1]),
      .sfraddr    (sfraddr),
      .sfrwe      (sfrwe)
      ); 
   
   //---------------------------------------------------------------
   // Compare/Capture Bit Port 0 Control
   //---------------------------------------------------------------
   CCU_PORT CCU_PORT_2
      (
      .clk        (clk),
      .rst        (rst),
      .compare    (com_int2),
      .ov         (th2_ov),
      .cocahl     (ccen[5:4]),
      .t2cm       (t2con[2]),
      .pout       (cc2_out_int),
      .sfrdatai   (sfrdatai[2]),
      .sfraddr    (sfraddr),
      .sfrwe      (sfrwe)
      ); 
   
   //---------------------------------------------------------------
   // Compare/Capture Bit Port 0 Control
   //---------------------------------------------------------------
   CCU_PORT CCU_PORT_3
      (
      .clk        (clk),
      .rst        (rst),
      .compare    (com_int3),
      .ov         (th2_ov),
      .cocahl     (ccen[7:6]),
      .t2cm       (t2con[2]),
      .pout       (cc3_out_int),
      .sfrdatai   (sfrdatai[3]),
      .sfraddr    (sfraddr),
      .sfrwe      (sfrwe)
      ); 
   
   //------------------------------------------------------------------
   // Compare Capture Enable Register 
   //------------------------------------------------------------------
   assign ccenreg = ccen ; 
   
   //------------------------------------------------------------------
   // Timer 2 external flag
   //   interrupt request flag
   //   high active output
   //------------------------------------------------------------------
   assign exf2 = t2ex_fall ; 
   
   //------------------------------------------------------------------
   // Timer 2 overflow output
   //   output for serial interface
   //   high active output
   //   active during single clk period
   //------------------------------------------------------------------
   assign tf2 = th2_ov ; 
   
   //------------------------------------------------------------------
   // Timer 2 clock
   // t0_clk is high active during single clk period
   //------------------------------------------------------------------
   assign t2_clk =
      ((t2con[7])) ? clk_ov24 :
      clk_ov12 ; 
   
   //------------------------------------------------------------------
   // Timer 2 low ordered byte clock
   // tl2_clk is high active during single clk period
   //------------------------------------------------------------------
   assign tl2_clk =
      (t2con[1:0] == 2'b01) ? t2_clk :
      (t2con[1:0] == 2'b10) ? t2_fall :
      (t2con[1:0] == 2'b11) ? t2_ff0 & t2_clk :
      1'b0 ; 
   
   //------------------------------------------------------------------
   // cc0 mode mask
   //------------------------------------------------------------------
   assign coca0_mode = ccen[1:0];
   
   //------------------------------------------------------------------
   // cc1 mode mask
   //------------------------------------------------------------------
   assign coca1_mode = ccen[3:2];   
   
   //------------------------------------------------------------------
   // cc2 mode mask
   //------------------------------------------------------------------
   assign coca2_mode = ccen[5:4];    
   
   //------------------------------------------------------------------
   // cc3 mode mask
   //------------------------------------------------------------------
   assign coca3_mode = ccen[7:6];   
   
   //------------------------------------------------------------------
   // counter2 mode mask
   //------------------------------------------------------------------   
   assign cnt2_mode = t2con[1:0];
   
   //------------------------------------------------------------------
   // reload of timer2 mode mask
   //------------------------------------------------------------------   
   assign rtm2_mode = t2con[4:3];
   
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : t2con_ccen_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      t2con <= T2CON_RV ; 
      ccen <= CCEN_RV ; 
      end
   else
      //--------------------------------
      // Special function register write
      //--------------------------------
      begin
      if (sfrwe & sfraddr == T2CON_ID)
         begin
         t2con <= sfrdatai ; 
         end 
      
      if (sfrwe & sfraddr == CCEN_ID)
         begin
         ccen <= sfrdatai ; 
         end 
      
      end  
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : cc1_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      ccl1 <= CCL1_RV ; 
      cch1 <= CCH1_RV ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Timer 2 Capture
      //--------------------------------
      begin
      if (ccen[3:2] == 2'b01 & cc1_rise)
         begin
         ccl1 <= tl2 ; 
         cch1 <= th2 ; 
         end 
      
      //--------------------------------
      // Special function register write
      //--------------------------------
      if (sfrwe & sfraddr == CCL1_ID)
         begin
         if (ccen[3:2] == 2'b11)
            begin
            ccl1 <= tl2 ; 
            cch1 <= th2 ; 
            end
         else
            begin
            ccl1 <= sfrdatai ; 
            end 
         end 
         
      if (sfrwe & sfraddr == CCH1_ID)
         begin
         cch1 <= sfrdatai ; 
         end 
      
      end  
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : cc2_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      ccl2 <= CCL2_RV ; 
      cch2 <= CCH2_RV ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Timer 2 Capture
      //--------------------------------
      begin
      if (ccen[5:4] == 2'b01 & cc2_rise)
         begin
         ccl2 <= tl2 ; 
         cch2 <= th2 ; 
         end 
      
      //--------------------------------
      // Special function register write
      //--------------------------------
      if (sfrwe & sfraddr == CCL2_ID)
         begin
         if (ccen[5:4] == 2'b11)
            begin
            ccl2 <= tl2 ; 
            cch2 <= th2 ; 
            end
         else
            begin
            ccl2 <= sfrdatai ; 
            end 
         end 
      
      if (sfrwe & sfraddr == CCH2_ID)
         begin
         cch2 <= sfrdatai ; 
         end 
      
      end  
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : cc3_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      ccl3 <= CCL3_RV ; 
      cch3 <= CCH3_RV ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Timer 2 Capture
      //--------------------------------
      begin
      if (ccen[7:6] == 2'b01 & cc3_rise)
         begin
         ccl3 <= tl2 ; 
         cch3 <= th2 ; 
         end 
      
      //--------------------------------
      // Special function register write
      //--------------------------------
      if (sfrwe & sfraddr == CCL3_ID)
         begin
         if (ccen[7:6] == 2'b11)
            begin
            ccl3 <= tl2 ; 
            cch3 <= th2 ; 
            end
         else
            begin
            ccl3 <= sfrdatai ; 
            end 
         end 
         
      if (sfrwe & sfraddr == CCH3_ID)
         begin
         cch3 <= sfrdatai ; 
         end 
      
      end  
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : crc_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      crcl <= CRCL_RV ; 
      crch <= CRCH_RV ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Timer 2 Capture
      //--------------------------------
      begin
      if (ccen[1:0] == 2'b01 & cc0_fall_rise)
         begin
         crcl <= tl2 ; 
         crch <= th2 ; 
         end 
      
      //--------------------------------
      // Special function register write
      //--------------------------------
      if (sfrwe & sfraddr == CRCL_ID)
         begin
         if (ccen[1:0] == 2'b11)
            begin
            crcl <= tl2 ; 
            crch <= th2 ; 
            end
         else
            begin
            crcl <= sfrdatai ; 
            end 
         end 
         
      if (sfrwe & sfraddr == CRCH_ID)
         begin
         crch <= sfrdatai ; 
         end 
      
      end  
   end 

   //------------------------------------------------------------------
   always @(tl2 or th2 or ccl1 or cch1 or ccl2 or cch2 or ccl3 or cch3 or 
            crcl or crch or ccen)
   //------------------------------------------------------------------
   begin : compare_proc
   //------------------------------------------------------------------
   case (ccen[1:0])
   2'b10 :
      begin
      if ((tl2 == crcl) & (th2 == crch))
         begin
         com_int0 = 1'b1 ; 
         end
      else
         begin
         com_int0 = 1'b0 ; 
         end 
      end
   
   default :
      begin
      com_int0 = 1'b0 ; 
      end
   
   endcase 
   
   case (ccen[3:2])
   2'b10 :
      begin
      if ((tl2 == ccl1) & (th2 == cch1))
         begin
         com_int1 = 1'b1 ; 
         end
      else
         begin
         com_int1 = 1'b0 ; 
         end 
      end
   
   default :
      begin
      com_int1 = 1'b0 ; 
      end
   
   endcase 
   
   case (ccen[5:4])
   2'b10 :
      begin
      if ((tl2 == ccl2) & (th2 == cch2))
         begin
         com_int2 = 1'b1 ; 
         end
      else
         begin