📄 ramsfrctrl.v
字号:
DEC_ADDR, ANL_ADDR_N,
ORL_ADDR_N, XRL_ADDR_N,
ANL_A_ADDR, ANL_ADDR_A,
ORL_A_ADDR, ORL_ADDR_A,
XRL_A_ADDR, XRL_ADDR_A,
MOV_A_ADDR, MOV_ADDR_A,
MOV_R0_ADDR, MOV_R1_ADDR,
MOV_R2_ADDR, MOV_R3_ADDR,
MOV_R4_ADDR, MOV_R5_ADDR,
MOV_R6_ADDR, MOV_R7_ADDR,
MOV_ADDR_R0, MOV_ADDR_R1,
MOV_ADDR_R2, MOV_ADDR_R3,
MOV_ADDR_R4, MOV_ADDR_R5,
MOV_ADDR_R6, MOV_ADDR_R7,
MOV_ADDR_N, MOV_ADDR_ADDR,
MOV_IR0_ADDR, MOV_IR1_ADDR,
PUSH, POP,
CJNE_A_ADDR, DJNZ_ADDR,
XCH_ADDR :
begin
if (mempsackint)
begin
ram_sfr_address <= memdatai ;
end
end
CLR_BIT, SETB_BIT,
ANL_C_BIT, ANL_C_NBIT,
ORL_C_BIT, ORL_C_NBIT,
MOV_C_BIT, MOV_BIT_C,
CPL_BIT, JBC_BIT,
JB_BIT, JNB_BIT :
begin
if (mempsackint)
begin
if (!(memdatai[7]))
begin
ram_sfr_address <= {4'b0010, memdatai[6:3]} ;
end
else
begin
ram_sfr_address <= {1'b1, memdatai[6:3], 3'b000} ;
end
end
end
RET, RETI,
ACALL_0, ACALL_1,
ACALL_2, ACALL_3,
ACALL_4, ACALL_5,
ACALL_6, ACALL_7,
LCALL :
begin
ram_sfr_address <= sp ;
end
endcase
end
2 :
begin
case (instr)
MOV_IR0_ADDR, MOV_IR1_ADDR :
begin
ram_sfr_address <= {3'b000, regsbank, 2'b00, instr[0]};
end
MOV_R0_ADDR, MOV_R1_ADDR,
MOV_R2_ADDR, MOV_R3_ADDR,
MOV_R4_ADDR, MOV_R5_ADDR,
MOV_R6_ADDR, MOV_R7_ADDR :
begin
ram_sfr_address <= {3'b000, regsbank, instr[2:0]} ;
end
MOV_ADDR_ADDR :
begin
if (mempsackint)
begin
ram_sfr_address <= memdatai ;
end
end
PUSH :
begin
ram_sfr_address <= sp ;
end
MOV_ADDR_IR0, MOV_ADDR_IR1 :
begin
ram_sfr_address <= datareg ;
end
endcase
end
3 :
begin
case (instr)
MOV_IR0_ADDR, MOV_IR1_ADDR :
begin
ram_sfr_address <= ramdatai ;
end
ACALL_0, ACALL_1,
ACALL_2, ACALL_3,
ACALL_4, ACALL_5,
ACALL_6, ACALL_7,
LCALL :
begin
ram_sfr_address <= sp ;
end
endcase
end
endcase
end
end
end
//------------------------------------------------------------------
always @(posedge clk)
begin : db_acc_write_proc
//------------------------------------------------------------------
if (rst)
//-----------------------------------
// Synchronous reset
//-----------------------------------
begin
db_accreg <= 1'b0 ;
end
else
//-----------------------------------
// Synchronous write
//-----------------------------------
begin
case (cycle)
1 :
begin
case (instr)
MOV_R0_A, MOV_R1_A,
MOV_R2_A, MOV_R3_A,
MOV_R4_A, MOV_R5_A,
MOV_R6_A, MOV_R7_A,
XCH_R0, XCH_R1,
XCH_R2, XCH_R3,
XCH_R4, XCH_R5,
XCH_R6, XCH_R7 :
begin
db_accreg <= 1'b1 ;
end
default :
begin
db_accreg <= 1'b0 ;
end
endcase
end
2 :
begin
case (instr)
MOV_ADDR_A, XCH_ADDR,
MOV_IR0_A, MOV_IR1_A,
XCH_IR0, XCH_IR1 :
begin
db_accreg <= 1'b1 ;
end
default :
begin
db_accreg <= 1'b0 ;
end
endcase
end
default :
begin
db_accreg <= 1'b0 ;
end
endcase
end
end
//------------------------------------------------------------------
always @(posedge clk)
begin : db_aluresult_write_proc
//------------------------------------------------------------------
if (rst)
//-----------------------------------
// Synchronous reset
//-----------------------------------
begin
db_aluresult <= 1'b0 ;
end
else
//-----------------------------------
// Synchronous write
//-----------------------------------
begin
case (cycle)
1 :
begin
case (instr)
DJNZ_R0, DJNZ_R1,
DJNZ_R2, DJNZ_R3,
DJNZ_R4, DJNZ_R5,
DJNZ_R6, DJNZ_R7,
INC_R0, INC_R1,
INC_R2, INC_R3,
INC_R4, INC_R5,
INC_R6, INC_R7,
DEC_R0, DEC_R1,
DEC_R2, DEC_R3,
DEC_R4, DEC_R5,
DEC_R6, DEC_R7 :
begin
db_aluresult <= 1'b1 ;
end
default :
begin
db_aluresult <= 1'b0 ;
end
endcase
end
2 :
begin
case (instr)
INC_ADDR, DEC_ADDR,
INC_IR0, INC_IR1,
DEC_IR0, DEC_IR1,
ANL_ADDR_A, ORL_ADDR_A,
XRL_ADDR_A, CLR_BIT,
SETB_BIT, CPL_BIT,
MOV_BIT_C :
begin
db_aluresult <= 1'b1 ;
end
default :
begin
db_aluresult <= 1'b0 ;
end
endcase
end
3 :
begin
case (instr)
ANL_ADDR_N, XRL_ADDR_N,
ORL_ADDR_N, JBC_BIT,
DJNZ_ADDR :
begin
db_aluresult <= 1'b1 ;
end
default :
begin
db_aluresult <= 1'b0 ;
end
endcase
end
default :
begin
db_aluresult <= 1'b0 ;
end
endcase
end
end
//------------------------------------------------------------------
always @(posedge clk)
begin : db_pclcreg_write_proc
//------------------------------------------------------------------
if (rst)
//-----------------------------------
// Synchronous reset
//-----------------------------------
begin
db_pclreg <= 1'b0 ;
end
else
//-----------------------------------
// Synchronous write
//-----------------------------------
begin
case (cycle)
2 :
begin
case (instr)
ACALL_0, ACALL_1,
ACALL_2, ACALL_3,
ACALL_4, ACALL_5,
ACALL_6, ACALL_7,
LCALL :
begin
db_pclreg <= 1'b1 ;
end
default :
begin
db_pclreg <= 1'b0 ;
end
endcase
end
default :
begin
db_pclreg <= 1'b0 ;
end
endcase
end
end
//------------------------------------------------------------------
always @(posedge clk)
begin : db_pchcreg_write_proc
//------------------------------------------------------------------
if (rst)
//-----------------------------------
// Synchronous reset
//-----------------------------------
begin
db_pchreg <= 1'b0 ;
end
else
//-----------------------------------
// Synchronous write
//-----------------------------------
begin
case (cycle)
4 :
begin
case (instr)
ACALL_0, ACALL_1,
ACALL_2, ACALL_3,
ACALL_4, ACALL_5,
ACALL_6, ACALL_7,
LCALL :
begin
db_pchreg <= 1'b1 ;
end
default :
begin
db_pchreg <= 1'b0 ;
end
endcase
end
default :
begin
db_pchreg <= 1'b0 ;
end
endcase
end
end
//------------------------------------------------------------------
always @(posedge clk)
begin : datareg_write_proc
//------------------------------------------------------------------
if (rst)
//-----------------------------------
// Synchronous reset
//-----------------------------------
begin
datareg <= DATAREG_RV;
end
else
//-----------------------------------
// Synchronous write
//-----------------------------------
begin
case (cycle)
1 :
begin
case (instr)
MOV_R0_N, MOV_R1_N,
MOV_R2_N, MOV_R3_N,
MOV_R4_N, MOV_R5_N,
MOV_R6_N, MOV_R7_N,
MOV_ADDR_IR0, MOV_ADDR_IR1,
MOV_IR0_N, MOV_IR1_N,
MOV_A_N :
begin
datareg <= memdatai ;
end
MOV_ADDR_R0, MOV_ADDR_R1,
MOV_ADDR_R2, MOV_⌨️ 快捷键说明
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