ramsfrctrl.v

8051的Verilog实现

      (
         mempsackint &
         (
            (memdatai == ACALL_0 & (codefetche | debugfetche)) |
            (memdatai == ACALL_1 & (codefetche | debugfetche)) |
            (memdatai == ACALL_2 & (codefetche | debugfetche)) |
            (memdatai == ACALL_3 & (codefetche | debugfetche)) |
            (memdatai == ACALL_4 & (codefetche | debugfetche)) |
            (memdatai == ACALL_5 & (codefetche | debugfetche)) |
            (memdatai == ACALL_6 & (codefetche | debugfetche)) |
            (memdatai == ACALL_7 & (codefetche | debugfetche)) |
            (memdatai == LCALL &   (codefetche | debugfetche)) |
            (intreq &              (codefetche | debugfetche)) |    // LCALL
            (instr == PUSH    & cycle == 1) |
            (instr == ACALL_0 & cycle == 1) |
            (instr == ACALL_1 & cycle == 1) |
            (instr == ACALL_2 & cycle == 1) |
            (instr == ACALL_3 & cycle == 1) |
            (instr == ACALL_4 & cycle == 1) |
            (instr == ACALL_5 & cycle == 1) |
            (instr == ACALL_6 & cycle == 1) |
            (instr == ACALL_7 & cycle == 1) |
            (instr == LCALL   & cycle == 1)
         )
      ) ? 1'b1 :
      1'b0 ; 
   
   //------------------------------------------------------------------
   // Stack Pointer decrement enable
   //------------------------------------------------------------------
   assign spdece =
      (
         (mempsackint &
            (
               (memdatai == RET &  (codefetche | debugfetche)) |
               (memdatai == RETI & (codefetche | debugfetche))
            )
         ) |
         (instr == RET & cycle == 1) |
         (instr == RETI & cycle == 1) |
         (instr == POP & cycle == 2)
      ) ? 1'b1 :
      1'b0 ; 
   
   //------------------------------------------------------------------
   // Stack Pointer increment vector
   //------------------------------------------------------------------
   assign sp_inc =
      (sfr_we & ram_sfr_address == {1'b1, SP_ID}) ? sfr_datao + 1'b1 :
      sp + 1'b1 ; 
   
   //------------------------------------------------------------------
   // Stack Pointer increment vector
   //------------------------------------------------------------------
   assign sp_dec =
      (sfr_we & ram_sfr_address == {1'b1, SP_ID}) ? sfr_datao - 1'b1 :
      sp - 1'b1 ; 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : sp_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      sp <= SP_RV ; 
      end
   else
      begin
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Special function register write
      //--------------------------------
      if (spince)
         begin
         sp <= sp_inc;
         end
      else
         begin
         if (spdece)
            begin
            sp <= sp_dec;
            end
         else
            begin
            if (sfr_we & ram_sfr_address[6:0]==SP_ID)
               begin
               sp <= sfr_datao;
               end
            end
         end
      end  
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : ram_oe_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      ram_oe <= 1'b0 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      begin
      if (mempsackint)
         begin
         if ((codefetche | debugfetche))
            begin
            case (memdatai)
            ADD_IR0, ADD_IR1,
            ADDC_IR0, ADDC_IR1,
            INC_IR0, INC_IR1,
            DEC_IR0, DEC_IR1,
            ANL_A_IR0, ANL_A_IR1,
            ORL_A_IR0, ORL_A_IR1,
            XRL_A_IR0, XRL_A_IR1,
            MOV_A_IR0, MOV_A_IR1,
            MOV_ADDR_IR0, MOV_ADDR_IR1,
            MOV_IR0_A, MOV_IR1_A,
            MOV_IR0_N, MOV_IR1_N,
            XCH_IR0, XCH_IR1,
            XCHD_IR0, XCHD_IR1,
            CJNE_IR0_N, CJNE_IR1_N,
            ADD_R0, ADD_R1,
            ADD_R2, ADD_R3,
            ADD_R4, ADD_R5,
            ADD_R6, ADD_R7,
            ADDC_R0, ADDC_R1,
            ADDC_R2, ADDC_R3,
            ADDC_R4, ADDC_R5,
            ADDC_R6, ADDC_R7,
            SUBB_IR0, SUBB_IR1,
            SUBB_R0, SUBB_R1,
            SUBB_R2, SUBB_R3,
            SUBB_R4, SUBB_R5,
            SUBB_R6, SUBB_R7,
            INC_R0, INC_R1,
            INC_R2, INC_R3,
            INC_R4, INC_R5,
            INC_R6, INC_R7,
            DEC_R0, DEC_R1,
            DEC_R2, DEC_R3,
            DEC_R4, DEC_R5,
            DEC_R6, DEC_R7,
            ANL_A_R0, ANL_A_R1,
            ANL_A_R2, ANL_A_R3,
            ANL_A_R4, ANL_A_R5,
            ANL_A_R6, ANL_A_R7,
            ORL_A_R0, ORL_A_R1,
            ORL_A_R2, ORL_A_R3,
            ORL_A_R4, ORL_A_R5,
            ORL_A_R6, ORL_A_R7,
            XRL_A_R0, XRL_A_R1,
            XRL_A_R2, XRL_A_R3,
            XRL_A_R4, XRL_A_R5,
            XRL_A_R6, XRL_A_R7,
            MOV_A_R0, MOV_A_R1,
            MOV_A_R2, MOV_A_R3,
            MOV_A_R4, MOV_A_R5,
            MOV_A_R6, MOV_A_R7,
            MOV_R0_A, MOV_R1_A,
            MOV_R2_A, MOV_R3_A,
            MOV_R4_A, MOV_R5_A,
            MOV_R6_A, MOV_R7_A,
            MOV_ADDR_R0, MOV_ADDR_R1,
            MOV_ADDR_R2, MOV_ADDR_R3,
            MOV_ADDR_R4, MOV_ADDR_R5,
            MOV_ADDR_R6, MOV_ADDR_R7,
            XCH_R0, XCH_R1,
            XCH_R2, XCH_R3,
            XCH_R4, XCH_R5,
            XCH_R6, XCH_R7,
            CJNE_R0_N, CJNE_R1_N,
            CJNE_R2_N, CJNE_R3_N,
            CJNE_R4_N, CJNE_R5_N,
            CJNE_R6_N, CJNE_R7_N,
            DJNZ_R0, DJNZ_R1,
            DJNZ_R2, DJNZ_R3,
            DJNZ_R4, DJNZ_R5,
            DJNZ_R6, DJNZ_R7,
            MOVX_A_IR0, MOVX_A_IR1,
            MOVX_IR0_A, MOVX_IR1_A,
            RET, RETI,
            POP :
               begin
               ram_oe <= 1'b1 ; 
               end
            
            default :
               begin
               ram_oe <= 1'b0 ; 
               end
            
            endcase 
            end
         else if (ram2memaddr)
            begin
            ram_oe <= 1'b1 ; 
            end
         else
            begin
            case (cycle)
            1 :
               begin
               case (instr)
               ADD_IR0, ADD_IR1,
               ADDC_IR0, ADDC_IR1,
               INC_IR0, INC_IR1,
               DEC_IR0, DEC_IR1,
               ORL_A_IR0, ORL_A_IR1,
               ANL_A_IR0, ANL_A_IR1,
               XRL_A_IR0, XRL_A_IR1,
               CJNE_IR0_N, CJNE_IR1_N,
               MOV_A_IR0, MOV_A_IR1,
               MOV_ADDR_IR0, MOV_ADDR_IR1,
               SUBB_IR0, SUBB_IR1,
               XCH_IR0, XCH_IR1,
               XCHD_IR0, XCHD_IR1,
               MOVX_A_IR0, MOVX_A_IR1,
               MOVX_IR0_A, MOVX_IR1_A,
               RET, RETI :
                  begin
                  ram_oe <= 1'b1 ; 
                  end
               ADD_ADDR, ADDC_ADDR,
               SUBB_ADDR, INC_ADDR,
               DEC_ADDR, ANL_A_ADDR,
               ORL_A_ADDR, XRL_A_ADDR,
               ANL_ADDR_A, ANL_ADDR_N,
               ORL_ADDR_A, ORL_ADDR_N,
               XRL_ADDR_A, XRL_ADDR_N,
               MOV_A_ADDR, MOV_R0_ADDR,
               MOV_R1_ADDR, MOV_R2_ADDR,
               MOV_R3_ADDR, MOV_R4_ADDR,
               MOV_R5_ADDR, MOV_R6_ADDR,
               MOV_R7_ADDR, MOV_ADDR_ADDR,
               MOV_IR0_ADDR, MOV_IR1_ADDR,
               CJNE_A_ADDR, DJNZ_ADDR,
               XCH_ADDR, PUSH, CLR_BIT,
               SETB_BIT, ANL_C_BIT,
               ANL_C_NBIT, ORL_C_BIT,
               ORL_C_NBIT, MOV_C_BIT,
               MOV_BIT_C, CPL_BIT,
               JBC_BIT, JB_BIT,
               JNB_BIT :
                  begin
                  if (!(memdatai[7]))
                     begin
                     ram_oe <= 1'b1 ; 
                     end
                  else
                     begin
                     ram_oe <= 1'b0 ; 
                     end 
                  end
               
               default :
                  begin
                  ram_oe <= 1'b0 ; 
                  end
               
               endcase 
               end
            
            2 :
               begin
               case (instr)
               MOV_IR0_ADDR, MOV_IR1_ADDR :
                  begin
                  ram_oe <= 1'b1 ; 
                  end
               
               default :
                  begin
                  ram_oe <= 1'b0 ; 
                  end
               
               endcase 
               end
            
            default :
               begin
               ram_oe <= 1'b0 ; 
               end
            
            endcase 
            end 
         end
      end
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : ram_we_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      ram_we <= 1'b0 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      begin
      if (mempsackint)
         begin
         case (cycle)
         1 :
            begin
            case (instr)
            DJNZ_R0, DJNZ_R1,
            DJNZ_R2, DJNZ_R3,
            DJNZ_R4, DJNZ_R5,
            DJNZ_R6, DJNZ_R7,
            INC_R0, INC_R1,
            INC_R2, INC_R3,
            INC_R4, INC_R5,
            INC_R6, INC_R7,
            DEC_R0, DEC_R1,
            DEC_R2, DEC_R3,
            DEC_R4, DEC_R5,
            DEC_R6, DEC_R7,
            MOV_R0_A, MOV_R1_A,
            MOV_R2_A, MOV_R3_A,
            MOV_R4_A, MOV_R5_A,
            MOV_R6_A, MOV_R7_A,
            MOV_R0_N, MOV_R1_N,
            MOV_R2_N, MOV_R3_N,
            MOV_R4_N, MOV_R5_N,
            MOV_R6_N, MOV_R7_N,
            XCH_R0, XCH_R1,
            XCH_R2, XCH_R3,
            XCH_R4, XCH_R5,
            XCH_R6, XCH_R7 :
               begin
               ram_we <= 1'b1 ; 
               end
            
            default :
               begin
               ram_we <= 1'b0 ; 
               end
            
            endcase 
            end
         
         2 :
            begin
            case (instr)
            INC_IR0, INC_IR1,
            DEC_IR0, DEC_IR1,
            MOV_IR0_A, MOV_IR1_A,
            MOV_IR0_N, MOV_IR1_N,
            XCH_IR0, XCH_IR1,
            XCHD_IR0, XCHD_IR1,
            ACALL_0, ACALL_1,
            ACALL_2, ACALL_3,
            ACALL_4, ACALL_5,
            ACALL_6, ACALL_7,
            LCALL :
               begin
               ram_we <= 1'b1 ; 
               end
            INC_ADDR, DEC_ADDR,
            ANL_ADDR_A, ORL_ADDR_A,
            XRL_ADDR_A, MOV_ADDR_A,
            MOV_ADDR_N, MOV_ADDR_R0,
            MOV_ADDR_R1, MOV_ADDR_R2,
            MOV_ADDR_R3, MOV_ADDR_R4,
            MOV_ADDR_R5, MOV_ADDR_R6,
            MOV_ADDR_R7, POP,
            XCH_ADDR, CLR_BIT,
            SETB_BIT, CPL_BIT,
            MOV_BIT_C :
               begin
               if (!(ram_sfr_address[7]))
                  begin
                  ram_we <= 1'b1 ; 
                  end
               else
                  begin
                  ram_we <= 1'b0 ; 
                  end 
               end
            
            default :
               begin
               ram_we <= 1'b0 ; 
               end
            
            endcase 
            end
         
         3 :