uart.v

带自适应波特率发生器UART实现

////////////////////////////////////////////////////////////////////////
//                                                                    
//  Abstract: Uart has an auto-tuning baud rate generator 
//                                                             
//  Module  : uart                              
//                                                                    
//  Version : ver 01.00                                  
//                                                                    
//  Modification History:                                            
//  Date By         Change Description                         
//  ----------------------------------------------------------------- 
//  2008/06/24  jackie                                         
//  YYYY/MM/DD  author     Revision content                           
//                                                                    
////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ns
module uart    (	 clk,
		         rst,				
		 // Transmitter
			 txd,
			 t_st,
			 sbuf_t,
			 ti,
		 // Receiver
			 rxd,
			 sbuf_r,
			 ri		
		 );

input			clk;
input			rst;

// Trasmitter
output		txd;
input		t_st;
input	[7:0]	sbuf_t;
output		ti;

// Receiver
input		rxd;
output	[7:0]	sbuf_r;
output		ri;

wire            clk;
wire            rst;
wire 		uart_clk;
wire	[7:0]	sbuf_r;
wire    [7:0]	sbuf_t;
wire		ri;
wire            ti;
wire            txd;
wire            t_st;

// Instantiate the Transmitter
u_xmit  iXMIT  (       
                  .uart_clk(uart_clk),
		  .rst(rst),
                  .clk( clk),
		  .txd(txd),
		  .t_st(t_st),
		  .sbuf_t(sbuf_t),
		  .ti(ti)
		);


// Instantiate the Receiver
u_rec iRECEIVER (
		   .rst(rst),
		   .uart_clk(uart_clk),
                   .clk(clk),				
		   .rxd(rxd),
		   .sbuf_r(sbuf_r),
		   .ri(ri)
		 );


// Instantiate the Baud Rate Generator
BAUD_GEN  baud   (
                   .rst(rst),
                   .clk(clk),
                   .rxd(rxd),
                   .baud_out(uart_clk)
                  );


endmodule