miba.map.eqn

VHDL语言设计的秒表

--operation mode is normal

D1L9 = E1L8 & E1L12 & E1L19 & !E1L16;


--D1L10 is deled:inst3|led~1199
--operation mode is normal

D1L10 = E1L8 # E1L16 # E1L19 # !E1L12;


--D1L11 is deled:inst3|led~1200
--operation mode is normal

D1L11 = E1L19 & (E1L16 # E1L8 & E1L12);


--D1L12 is deled:inst3|led~1201
--operation mode is normal

D1L12 = D1L9 # D1L10 & (!D1L11);


--D1L13 is deled:inst3|led~1202
--operation mode is normal

D1L13 = E1L8 & (E1L12 & (E1L19) # !E1L12 & E1L16) # !E1L8 & E1L16 & (E1L12 # E1L19);


--D1L14 is deled:inst3|led~1203
--operation mode is normal

D1L14 = D1L5 # !D1L3 & !D1L13;


--D1L15 is deled:inst3|led~1204
--operation mode is normal

D1L15 = !E1L12 & !E1L19 & (E1L8 $ E1L16);


--D1L16 is deled:inst3|led~1205
--operation mode is normal

D1L16 = D1L11 & D1L9 # !D1L11 & (D1L15);


--F1_enmin is second:inst5|enmin
--operation mode is normal

F1_enmin_lut_out = F1L18 & F1_count[6] & (F1_count[5] $ !F1_enmin) # !F1L18 & (F1_enmin);
F1_enmin = DFFEAS(F1_enmin_lut_out, B1_ensec, VCC, , , , , , );


--A1L12 is rtl~422
--operation mode is normal

A1L12 = C1_count[0] & C1_count[3] & !C1_count[1] & !C1_count[2];


--C1L4 is minute:inst2|count[0]~301
--operation mode is normal

C1L4 = C1_count[6] & (C1_count[5] # C1_count[4] & A1L12);


--B1_ensec is msecond:inst|ensec
--operation mode is normal

B1_ensec_lut_out = B1L22 & A1L24 & (B1_ensec # B1L21) # !B1L22 & (B1_ensec);
B1_ensec = DFFEAS(B1_ensec_lut_out, A1L11, VCC, , , , , , );


--A1L13 is rtl~423
--operation mode is normal

A1L13 = F1_count[0] & F1_count[3] & !F1_count[1] & !F1_count[2];


--F1L4 is second:inst5|count[0]~331
--operation mode is normal

F1L4 = F1_count[6] & (F1_count[5] # F1_count[4] & A1L13);


--G1_enter[31] is fenpin:inst10|enter[31]
--operation mode is normal

G1_enter[31]_lut_out = G1L1;
G1_enter[31] = DFFEAS(G1_enter[31]_lut_out, clk, VCC, , , , , , );


--G1_enter[30] is fenpin:inst10|enter[30]
--operation mode is normal

G1_enter[30]_lut_out = G1L2;
G1_enter[30] = DFFEAS(G1_enter[30]_lut_out, clk, VCC, , , , , , );


--G1_enter[29] is fenpin:inst10|enter[29]
--operation mode is normal

G1_enter[29]_lut_out = G1L4;
G1_enter[29] = DFFEAS(G1_enter[29]_lut_out, clk, VCC, , , , , , );


--G1_enter[28] is fenpin:inst10|enter[28]
--operation mode is normal

G1_enter[28]_lut_out = G1L6;
G1_enter[28] = DFFEAS(G1_enter[28]_lut_out, clk, VCC, , , , , , );


--A1L14 is rtl~424
--operation mode is normal

A1L14 = !G1_enter[31] & !G1_enter[30] & !G1_enter[29] & !G1_enter[28];


--G1_enter[27] is fenpin:inst10|enter[27]
--operation mode is normal

G1_enter[27]_lut_out = G1L8;
G1_enter[27] = DFFEAS(G1_enter[27]_lut_out, clk, VCC, , , , , , );


--G1_enter[26] is fenpin:inst10|enter[26]
--operation mode is normal

G1_enter[26]_lut_out = G1L10;
G1_enter[26] = DFFEAS(G1_enter[26]_lut_out, clk, VCC, , , , , , );


--G1_enter[25] is fenpin:inst10|enter[25]
--operation mode is normal

G1_enter[25]_lut_out = G1L12;
G1_enter[25] = DFFEAS(G1_enter[25]_lut_out, clk, VCC, , , , , , );


--G1_enter[24] is fenpin:inst10|enter[24]
--operation mode is normal

G1_enter[24]_lut_out = G1L14;
G1_enter[24] = DFFEAS(G1_enter[24]_lut_out, clk, VCC, , , , , , );


--A1L15 is rtl~425
--operation mode is normal

A1L15 = !G1_enter[27] & !G1_enter[26] & !G1_enter[25] & !G1_enter[24];


--G1_enter[23] is fenpin:inst10|enter[23]
--operation mode is normal

G1_enter[23]_lut_out = G1L16;
G1_enter[23] = DFFEAS(G1_enter[23]_lut_out, clk, VCC, , , , , , );


--G1_enter[22] is fenpin:inst10|enter[22]
--operation mode is normal

G1_enter[22]_lut_out = G1L18;
G1_enter[22] = DFFEAS(G1_enter[22]_lut_out, clk, VCC, , , , , , );


--G1_enter[21] is fenpin:inst10|enter[21]
--operation mode is normal

G1_enter[21]_lut_out = G1L20;
G1_enter[21] = DFFEAS(G1_enter[21]_lut_out, clk, VCC, , , , , , );


--G1_enter[20] is fenpin:inst10|enter[20]
--operation mode is normal

G1_enter[20]_lut_out = G1L22;
G1_enter[20] = DFFEAS(G1_enter[20]_lut_out, clk, VCC, , , , , , );


--A1L16 is rtl~426
--operation mode is normal

A1L16 = !G1_enter[23] & !G1_enter[22] & !G1_enter[21] & !G1_enter[20];


--G1_enter[19] is fenpin:inst10|enter[19]
--operation mode is normal

G1_enter[19]_lut_out = G1L24;
G1_enter[19] = DFFEAS(G1_enter[19]_lut_out, clk, VCC, , , , , , );


--G1_enter[18] is fenpin:inst10|enter[18]
--operation mode is normal

G1_enter[18]_lut_out = G1L26;
G1_enter[18] = DFFEAS(G1_enter[18]_lut_out, clk, VCC, , , , , , );


--G1_enter[17] is fenpin:inst10|enter[17]
--operation mode is normal

G1_enter[17]_lut_out = G1L28;
G1_enter[17] = DFFEAS(G1_enter[17]_lut_out, clk, VCC, , , , , , );


--G1_enter[16] is fenpin:inst10|enter[16]
--operation mode is normal

G1_enter[16]_lut_out = G1L30;
G1_enter[16] = DFFEAS(G1_enter[16]_lut_out, clk, VCC, , , , , , );


--A1L17 is rtl~427
--operation mode is normal

A1L17 = !G1_enter[19] & !G1_enter[18] & !G1_enter[17] & !G1_enter[16];


--A1L18 is rtl~428
--operation mode is normal

A1L18 = A1L14 & A1L15 & A1L16 & A1L17;


--G1_enter[15] is fenpin:inst10|enter[15]
--operation mode is normal

G1_enter[15]_lut_out = G1L32;
G1_enter[15] = DFFEAS(G1_enter[15]_lut_out, clk, VCC, , , , , , );


--G1_enter[14] is fenpin:inst10|enter[14]
--operation mode is normal

G1_enter[14]_lut_out = G1L34;
G1_enter[14] = DFFEAS(G1_enter[14]_lut_out, clk, VCC, , , , , , );


--A1L19 is rtl~429
--operation mode is normal

A1L19 = !G1_enter[15] & !G1_enter[14];


--G1_enter[11] is fenpin:inst10|enter[11]
--operation mode is normal

G1_enter[11]_lut_out = G1L36;
G1_enter[11] = DFFEAS(G1_enter[11]_lut_out, clk, VCC, , , , , , );


--G1_enter[10] is fenpin:inst10|enter[10]
--operation mode is normal

G1_enter[10]_lut_out = G1L38;
G1_enter[10] = DFFEAS(G1_enter[10]_lut_out, clk, VCC, , , , , , );


--G1_enter[9] is fenpin:inst10|enter[9]
--operation mode is normal

G1_enter[9]_lut_out = G1L40;
G1_enter[9] = DFFEAS(G1_enter[9]_lut_out, clk, VCC, , , , , , );


--G1_enter[8] is fenpin:inst10|enter[8]
--operation mode is normal

G1_enter[8]_lut_out = G1L42;
G1_enter[8] = DFFEAS(G1_enter[8]_lut_out, clk, VCC, , , , , , );


--A1L20 is rtl~430
--operation mode is normal

A1L20 = !G1_enter[11] & !G1_enter[10] & !G1_enter[9] & !G1_enter[8];


--G1_enter[13] is fenpin:inst10|enter[13]
--operation mode is normal

G1_enter[13]_lut_out = G1L44;
G1_enter[13] = DFFEAS(G1_enter[13]_lut_out, clk, VCC, , , , , , );


--G1_enter[12] is fenpin:inst10|enter[12]
--operation mode is normal

G1_enter[12]_lut_out = G1L46;
G1_enter[12] = DFFEAS(G1_enter[12]_lut_out, clk, VCC, , , , , , );


--A1L21 is rtl~431
--operation mode is normal

A1L21 = A1L19 & A1L20 & !G1_enter[13] & !G1_enter[12];


--G1_enter[5] is fenpin:inst10|enter[5]
--operation mode is normal

G1_enter[5]_lut_out = G1L48 & (!A1L11);
G1_enter[5] = DFFEAS(G1_enter[5]_lut_out, clk, VCC, , , , , , );


--G1_enter[7] is fenpin:inst10|enter[7]
--operation mode is normal

G1_enter[7]_lut_out = G1L50;
G1_enter[7] = DFFEAS(G1_enter[7]_lut_out, clk, VCC, , , , , , );


--G1_enter[6] is fenpin:inst10|enter[6]
--operation mode is normal

G1_enter[6]_lut_out = G1L52;
G1_enter[6] = DFFEAS(G1_enter[6]_lut_out, clk, VCC, , , , , , );


--G1_enter[4] is fenpin:inst10|enter[4]
--operation mode is normal

G1_enter[4]_lut_out = G1L54;
G1_enter[4] = DFFEAS(G1_enter[4]_lut_out, clk, VCC, , , , , , );


--A1L22 is rtl~432
--operation mode is normal

A1L22 = G1_enter[5] & !G1_enter[7] & !G1_enter[6] & !G1_enter[4];


--G1_enter[3] is fenpin:inst10|enter[3]
--operation mode is normal

G1_enter[3]_lut_out = G1L56 & (!A1L11);
G1_enter[3] = DFFEAS(G1_enter[3]_lut_out, clk, VCC, , , , , , );


--G1_enter[2] is fenpin:inst10|enter[2]
--operation mode is normal

G1_enter[2]_lut_out = G1L58;
G1_enter[2] = DFFEAS(G1_enter[2]_lut_out, clk, VCC, , , , , , );


--G1_enter[1] is fenpin:inst10|enter[1]
--operation mode is normal

G1_enter[1]_lut_out = G1L60;
G1_enter[1] = DFFEAS(G1_enter[1]_lut_out, clk, VCC, , , , , , );


--G1_enter[0] is fenpin:inst10|enter[0]
--operation mode is normal

G1_enter[0]_lut_out = G1L62 & (!A1L11);
G1_enter[0] = DFFEAS(G1_enter[0]_lut_out, clk, VCC, , , , , , );


--A1L23 is rtl~433
--operation mode is normal

A1L23 = G1_enter[3] & !G1_enter[2] & !G1_enter[1] & !G1_enter[0];


--A1L11 is rtl~6
--operation mode is normal

A1L11 = A1L18 & A1L21 & A1L22 & A1L23;


--B1L4 is msecond:inst|count[0]~366
--operation mode is normal

B1L4 = !B1_count[5] & !B1_count[6];


--A1L24 is rtl~434
--operation mode is normal

A1L24 = B1_count[0] & B1_count[3] & !B1_count[1] & !B1_count[2];


--B1L5 is msecond:inst|count[0]~367
--operation mode is normal

B1L5 = B1_count[7] & (B1_count[4] & A1L24 # !B1L4);


--B1L20 is msecond:inst|ensec~271
--operation mode is normal

B1L20 = reset & set;


--F1L17 is second:inst5|enmin~201
--operation mode is normal

F1L17 = F1_count[4] & reset & set;


--F1L18 is second:inst5|enmin~202
--operation mode is normal

F1L18 = A1L13 & (!F1_enmin & F1L17) # !A1L13 & B1L20 & F1_enmin;


--B1L21 is msecond:inst|ensec~272
--operation mode is normal

B1L21 = B1_count[4] & B1_count[7] & !B1_count[5] & !B1_count[6];


--B1L22 is msecond:inst|ensec~273
--operation mode is normal

B1L22 = B1L20 & (!B1_count[5] & !B1_count[6] # !B1_count[7]);


--G1L1 is fenpin:inst10|add~481
--operation mode is normal

G1L1_carry_eqn = G1L3;
G1L1 = G1_enter[31] $ (G1L1_carry_eqn);


--G1L2 is fenpin:inst10|add~486
--operation mode is arithmetic

G1L2_carry_eqn = G1L5;
G1L2 = G1_enter[30] $ (!G1L2_carry_eqn);

--G1L3 is fenpin:inst10|add~488
--operation mode is arithmetic

G1L3 = CARRY(G1_enter[30] & (!G1L5));