miaobiao.fit.qmsg

VHDL语言设计的秒表

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jun 07 01:42:28 2008 " "Info: Processing started: Sat Jun 07 01:42:28 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off miaobiao -c miaobiao " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off miaobiao -c miaobiao" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "miaobiao EP1C12Q240C8 " "Info: Selected device EP1C12Q240C8 for design \"miaobiao\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6Q240C8 " "Info: Device EP1C6Q240C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock " "Info: Automatically promoted signal \"clk\" to use Global clock" {  } { { "miaobiao.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/miaobiao/miaobiao.bdf" { { 40 0 168 56 "clk" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "clk " "Info: Pin \"clk\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "miaobiao.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/miaobiao/miaobiao.bdf" { { 40 0 168 56 "clk" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "C:/Documents and Settings/Administrator/桌面/miaobiao/miaobiao.fld" "" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/miaobiao.fld" "" "" { clk } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "msecond:inst1\|ensec Global clock " "Info: Automatically promoted some destinations of signal \"msecond:inst1\|ensec\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "msecond:inst1\|ensec " "Info: Destination \"msecond:inst1\|ensec\" may be non-global or may not use global clock" {  } { { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 7 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "msecond:inst1\|ensec~190 " "Info: Destination \"msecond:inst1\|ensec~190\" may be non-global or may not use global clock" {  } { { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 7 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 7 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "second:inst2\|enmin Global clock " "Info: Automatically promoted some destinations of signal \"second:inst2\|enmin\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "second:inst2\|enmin " "Info: Destination \"second:inst2\|enmin\" may be non-global or may not use global clock" {  } { { "second.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/second.vhd" 7 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "second:inst2\|enmin~178 " "Info: Destination \"second:inst2\|enmin~178\" may be non-global or may not use global clock" {  } { { "second.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/second.vhd" 7 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "second.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/second.vhd" 7 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clkdsp Global clock " "Info: Automatically promoted signal \"clkdsp\" to use Global clock" {  } { { "miaobiao.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/miaobiao/miaobiao.bdf" { { 120 -24 144 136 "clkdsp" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "clkdsp " "Info: Pin \"clkdsp\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "miaobiao.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/miaobiao/miaobiao.bdf" { { 120 -24 144 136 "clkdsp" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clkdsp" } } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { clkdsp } "NODE_NAME" } "" } } { "C:/Documents and Settings/Administrator/桌面/miaobiao/miaobiao.fld" "" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/miaobiao.fld" "" "" { clkdsp } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "reset Global clock " "Info: Automatically promoted some destinations of signal \"reset\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "msecond:inst1\|ensec " "Info: Destination \"msecond:inst1\|ensec\" may be non-global or may not use global clock" {  } { { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 7 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "second:inst2\|enmin " "Info: Destination \"second:inst2\|enmin\" may be non-global or may not use global clock" {  } { { "second.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/second.vhd" 7 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "msecond:inst1\|ensec~4 " "Info: Destination \"msecond:inst1\|ensec~4\" may be non-global or may not use global clock" {  } { { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 7 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "miaobiao.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/miaobiao/miaobiao.bdf" { { 56 0 168 72 "reset" "" } } } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "reset " "Info: Pin \"reset\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "miaobiao.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/miaobiao/miaobiao.bdf" { { 56 0 168 72 "reset" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "reset" } } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { reset } "NODE_NAME" } "" } } { "C:/Documents and Settings/Administrator/桌面/miaobiao/miaobiao.fld" "" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/miaobiao.fld" "" "" { reset } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "msecond:inst1\|ensec~4 Global clock " "Info: Automatically promoted signal \"msecond:inst1\|ensec~4\" to use Global clock" {  } { { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 7 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0 0 "Started Fast Input/Output/OE register processing" 0 0}