miba.tan.qmsg

VHDL语言设计的秒表

{ "Info" "ITDB_TSU_RESULT" "msecond:inst\|ensec set clk -3.463 ns register " "Info: tsu for register \"msecond:inst\|ensec\" (data pin = \"set\", clock pin = \"clk\") is -3.463 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.721 ns + Longest pin register " "Info: + Longest pin to register delay is 11.721 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns set 1 PIN PIN_4 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_4; Fanout = 24; PIN Node = 'set'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "" { set } "NODE_NAME" } "" } } { "miba.bdf" "" { Schematic "D:/miaobiao/miba.bdf" { { 160 32 200 176 "set" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.527 ns) + CELL(0.590 ns) 8.586 ns msecond:inst\|ensec~271 2 COMB LC_X11_Y22_N2 2 " "Info: 2: + IC(6.527 ns) + CELL(0.590 ns) = 8.586 ns; Loc. = LC_X11_Y22_N2; Fanout = 2; COMB Node = 'msecond:inst\|ensec~271'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "7.117 ns" { set msecond:inst|ensec~271 } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "D:/miaobiao/msecond.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.228 ns) + CELL(0.442 ns) 10.256 ns msecond:inst\|ensec~273 3 COMB LC_X11_Y21_N5 1 " "Info: 3: + IC(1.228 ns) + CELL(0.442 ns) = 10.256 ns; Loc. = LC_X11_Y21_N5; Fanout = 1; COMB Node = 'msecond:inst\|ensec~273'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "1.670 ns" { msecond:inst|ensec~271 msecond:inst|ensec~273 } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "D:/miaobiao/msecond.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.727 ns) + CELL(0.738 ns) 11.721 ns msecond:inst\|ensec 4 REG LC_X11_Y21_N8 9 " "Info: 4: + IC(0.727 ns) + CELL(0.738 ns) = 11.721 ns; Loc. = LC_X11_Y21_N8; Fanout = 9; REG Node = 'msecond:inst\|ensec'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "1.465 ns" { msecond:inst|ensec~273 msecond:inst|ensec } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "D:/miaobiao/msecond.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.239 ns ( 27.63 % ) " "Info: Total cell delay = 3.239 ns ( 27.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.482 ns ( 72.37 % ) " "Info: Total interconnect delay = 8.482 ns ( 72.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "11.721 ns" { set msecond:inst|ensec~271 msecond:inst|ensec~273 msecond:inst|ensec } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.721 ns" { set set~out0 msecond:inst|ensec~271 msecond:inst|ensec~273 msecond:inst|ensec } { 0.000ns 0.000ns 6.527ns 1.228ns 0.727ns } { 0.000ns 1.469ns 0.590ns 0.442ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "msecond.vhd" "" { Text "D:/miaobiao/msecond.vhd" 7 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 15.221 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 15.221 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_2 35 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 35; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "miba.bdf" "" { Schematic "D:/miaobiao/miba.bdf" { { 16 -104 64 32 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.027 ns) + CELL(0.935 ns) 8.431 ns fenpin:inst10\|enter\[13\] 2 REG LC_X27_Y13_N7 4 " "Info: 2: + IC(6.027 ns) + CELL(0.935 ns) = 8.431 ns; Loc. = LC_X27_Y13_N7; Fanout = 4; REG Node = 'fenpin:inst10\|enter\[13\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "6.962 ns" { clk fenpin:inst10|enter[13] } "NODE_NAME" } "" } } { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.378 ns) 8.809 ns rtl~431 3 COMB LC_X27_Y13_N7 1 " "Info: 3: + IC(0.000 ns) + CELL(0.378 ns) = 8.809 ns; Loc. = LC_X27_Y13_N7; Fanout = 1; COMB Node = 'rtl~431'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "0.378 ns" { fenpin:inst10|enter[13] rtl~431 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 9.105 ns rtl~6 4 COMB LC_X27_Y13_N8 12 " "Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 9.105 ns; Loc. = LC_X27_Y13_N8; Fanout = 12; COMB Node = 'rtl~6'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "0.296 ns" { rtl~431 rtl~6 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.405 ns) + CELL(0.711 ns) 15.221 ns msecond:inst\|ensec 5 REG LC_X11_Y21_N8 9 " "Info: 5: + IC(5.405 ns) + CELL(0.711 ns) = 15.221 ns; Loc. = LC_X11_Y21_N8; Fanout = 9; REG Node = 'msecond:inst\|ensec'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "6.116 ns" { rtl~6 msecond:inst|ensec } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "D:/miaobiao/msecond.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.607 ns ( 23.70 % ) " "Info: Total cell delay = 3.607 ns ( 23.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.614 ns ( 76.30 % ) " "Info: Total interconnect delay = 11.614 ns ( 76.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "15.221 ns" { clk fenpin:inst10|enter[13] rtl~431 rtl~6 msecond:inst|ensec } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "15.221 ns" { clk clk~out0 fenpin:inst10|enter[13] rtl~431 rtl~6 msecond:inst|ensec } { 0.000ns 0.000ns 6.027ns 0.000ns 0.182ns 5.405ns } { 0.000ns 1.469ns 0.935ns 0.378ns 0.114ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "11.721 ns" { set msecond:inst|ensec~271 msecond:inst|ensec~273 msecond:inst|ensec } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.721 ns" { set set~out0 msecond:inst|ensec~271 msecond:inst|ensec~273 msecond:inst|ensec } { 0.000ns 0.000ns 6.527ns 1.228ns 0.727ns } { 0.000ns 1.469ns 0.590ns 0.442ns 0.738ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "15.221 ns" { clk fenpin:inst10|enter[13] rtl~431 rtl~6 msecond:inst|ensec } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "15.221 ns" { clk clk~out0 fenpin:inst10|enter[13] rtl~431 rtl~6 msecond:inst|ensec } { 0.000ns 0.000ns 6.027ns 0.000ns 0.182ns 5.405ns } { 0.000ns 1.469ns 0.935ns 0.378ns 0.114ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk led\[1\] minute:inst2\|count\[4\] 43.073 ns register " "Info: tco from clock \"clk\" to destination pin \"led\[1\]\" through register \"minute:inst2\|count\[4\]\" is 43.073 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 30.026 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 30.026 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_2 35 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 35; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "miba.bdf" "" { Schematic "D:/miaobiao/miba.bdf" { { 16 -104 64 32 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.026 ns) + CELL(0.935 ns) 8.430 ns fenpin:inst10\|enter\[22\] 2 REG LC_X26_Y12_N2 4 " "Info: 2: + IC(6.026 ns) + CELL(0.935 ns) = 8.430 ns; Loc. = LC_X26_Y12_N2; Fanout = 4; REG Node = 'fenpin:inst10\|enter\[22\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "6.961 ns" { clk fenpin:inst10|enter[22] } "NODE_NAME" } "" } } { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.523 ns) + CELL(0.590 ns) 9.543 ns rtl~426 3 COMB LC_X26_Y12_N9 1 " "Info: 3: + IC(0.523 ns) + CELL(0.590 ns) = 9.543 ns; Loc. = LC_X26_Y12_N9; Fanout = 1; COMB Node = 'rtl~426'" {  } { { "c:/altera/quartus51/bin/Report_Window_01