miba.tan.qmsg

VHDL语言设计的秒表

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "43 " "Warning: Found 43 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[2\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[2\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[0\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[0\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[1\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[1\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[3\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[3\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[7\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[7\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[4\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[4\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[6\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[6\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[5\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[5\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[13\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[13\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[13\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[12\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[12\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[12\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[11\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[11\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[11\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~430 " "Info: Detected gated clock \"rtl~430\" as buffer" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~430" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[8\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[8\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[8\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[9\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[9\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[9\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[10\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[10\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[10\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[15\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[15\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[15\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~429 " "Info: Detected gated clock \"rtl~429\" as buffer" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~429" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[14\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[14\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[14\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[19\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[19\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[19\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~427 " "Info: Detected gated clock \"rtl~427\" as buffer" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~427" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[16\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[16\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[16\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[17\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[17\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[17\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[18\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[18\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[18\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[23\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[23\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[23\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~426 " "Info: Detected gated clock \"rtl~426\" as buffer" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~426" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[20\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[20\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[20\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[21\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[21\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[21\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[22\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[22\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[22\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[27\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[27\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[27\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~425 " "Info: Detected gated clock \"rtl~425\" as buffer" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~425" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[24\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[24\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[24\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[25\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[25\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[25\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[26\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[26\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[26\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[31\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[31\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[31\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~424 " "Info: Detected gated clock \"rtl~424\" as buffer" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~424" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[28\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[28\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[28\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[29\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[29\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[29\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst10\|enter\[30\] " "Info: Detected ripple clock \"fenpin:inst10\|enter\[30\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst10\|enter\[30\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~431 " "Info: Detected gated clock \"rtl~431\" as buffer" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~431" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~433 " "Info: Detected gated clock \"rtl~433\" as buffer" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~433" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~432 " "Info: Detected gated clock \"rtl~432\" as buffer" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~432" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "msecond:inst\|ensec " "Info: Detected ripple clock \"msecond:inst\|ensec\" as buffer" {  } { { "msecond.vhd" "" { Text "D:/miaobiao/msecond.vhd" 7 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "msecond:inst\|ensec" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "second:inst5\|enmin " "Info: Detected ripple clock \"second:inst5\|enmin\" as buffer" {  } { { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 7 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "second:inst5\|enmin" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register second:inst5\|count\[4\] register second:inst5\|enmin 122.34 MHz 8.174 ns Internal " "Info: Clock \"clk\" has Internal fmax of 122.34 MHz between source register \"second:inst5\|count\[4\]\" and destination register \"second:inst5\|enmin\" (period= 8.174 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.748 ns + Longest register register " "Info: + Longest register to register delay is 4.748 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns second:inst5\|count\[4\] 1 REG LC_X11_Y20_N5 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y20_N5; Fanout = 6; REG Node = 'second:inst5\|count\[4\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "" { second:inst5|count[4] } "NODE_NAME" } "" } } { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.261 ns) + CELL(0.114 ns) 1.375 ns second:inst5\|enmin~201 2 COMB LC_X11_Y22_N4 1 " "Info: 2: + IC(1.261 ns) + CELL(0.114 ns) = 1.375 ns; Loc. = LC_X11_Y22_N4; Fanout = 1; COMB Node = 'second:inst5\|enmin~201'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "1.375 ns" { second:inst5|count[4] second:inst5|enmin~201 } "NODE_NAME" } "" } } { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.236 ns) + CELL(0.292 ns) 2.903 ns second:inst5\|enmin~202 3 COMB LC_X11_Y20_N9 1 " "Info: 3: + IC(1.236 ns) + CELL(0.292 ns) = 2.903 ns; Loc. = LC_X11_Y20_N9; Fanout = 1; COMB Node = 'second:inst5\|enmin~202'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "1.528 ns" { second:inst5|enmin~201 second:inst5|enmin~202 } "NODE_NAME" } "" } } { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.107 ns) + CELL(0.738 ns) 4.748 ns second:inst5\|enmin 4 REG LC_X9_Y20_N0 9 " "Info: 4: + IC(1.107 ns) + CELL(0.738 ns) = 4.748 ns; Loc. = LC_X9_Y20_N0; Fanout = 9; REG Node = 'second:inst5\|enmin'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "1.845 ns" { second:inst5|enmin~202 second:inst5|enmin } "NODE_NAME" } "" } } { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.144 ns ( 24.09 % ) " "Info: Total cell delay = 1.144 ns ( 24.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.604 ns ( 75.91 % ) " "Info: Total interconnect delay = 3.604 ns ( 75.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "4.748 ns" { second:inst5|count[4] second:inst5|enmin~201 second:inst5|enmin~202 second:inst5|enmin } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.748 ns" { second:inst5|count[4] second:inst5|enmin~201 second:inst5|enmin~202 second:inst5|enmin } { 0.000ns 1.261ns 1.236ns 1.107ns } { 0.000ns 0.114ns 0.292ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.165 ns - Smallest " "Info: - Smallest clock skew is -3.165 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 21.066 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 21.066 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_2 35 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 35; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "miba.bdf" "" { Schematic "D:/miaobiao/miba.bdf" { { 16 -104 64 32 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.027 ns) + CELL(0.935 ns) 8.431 ns fenpin:inst10\|enter\[13\] 2 REG LC_X27_Y13_N7 4 " "Info: 2: + IC(6.027 ns) + CELL(0.935 ns) = 8.431 ns; Loc. = LC_X27_Y13_N7; Fanout = 4; REG Node = 'fenpin:inst10\|enter\[13\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "6.962 ns" { clk fenpin:inst10|enter[13] } "NODE_NAME" } "" } } { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.378 ns) 8.809 ns rtl~431 3 COMB LC_X27_Y13_N7 1 " "Info: 3: + IC(0.000 ns) + CELL(0.378 ns) = 8.809 ns; Loc. = LC_X27_Y13_N7; Fanout = 1; COMB Node = 'rtl~431'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "0.378 ns" { fenpin:inst10|enter[13] rtl~431 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 9.105 ns rtl~6 4 COMB LC_X27_Y13_N8 12 " "Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 9.105 ns; Loc. = LC_X27_Y13_N8; Fanout = 12; COMB Node = 'rtl~6'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "0.296 ns" { rtl~431 rtl~6 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.405 ns) + CELL(0.935 ns) 15.445 ns msecond:inst\|ensec 5 REG LC_X11_Y21_N8 9 " "Info: 5: + IC(5.405 ns) + CELL(0.935 ns) = 15.445 ns; Loc. = LC_X11_Y21_N8; Fanout = 9; REG Node = 'msecond:inst\|ensec'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "6.340 ns" { rtl~6 msecond:inst|ensec } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "D:/miaobiao/msecond.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.910 ns) + CELL(0.711 ns) 21.066 ns second:inst5\|enmin 6 REG LC_X9_Y20_N0 9 " "Info: 6: + IC(4.910 ns) + CELL(0.711 ns) = 21.066 ns; Loc. = LC_X9_Y20_N0; Fanout = 9; REG Node = 'second:inst5\|enmin'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "5.621 ns" { msecond:inst|ensec second:inst5|enmin } "NODE_NAME" } "" } } { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.542 ns ( 21.56 % ) " "Info: Total cell delay = 4.542 ns ( 21.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "16.524 ns ( 78.44 % ) " "Info: Total interconnect delay = 16.524 ns ( 78.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "21.066 ns" { clk fenpin:inst10|enter[13] rtl~431 rtl~6 msecond:inst|ensec second:inst5|enmin } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "21.066 ns" { clk clk~out0 fenpin:inst10|enter[13] rtl~431 rtl~6 msecond:inst|ensec second:inst5|enmin } { 0.000ns 0.000ns 6.027ns 0.000ns 0.182ns 5.405ns 4.910ns } { 0.000ns 1.469ns 0.935ns 0.378ns 0.114ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 24.231 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 24.231 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_2 35 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 35; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "miba.bdf" "" { Schematic "D:/miaobiao/miba.bdf" { { 16 -104 64 32 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.026 ns) + CELL(0.935 ns) 8.430 ns fenpin:inst10\|enter\[22\] 2 REG LC_X26_Y12_N2 4 " "Info: 2: + IC(6.026 ns) + CELL(0.935 ns) = 8.430 ns; Loc. = LC_X26_Y12_N2; Fanout = 4; REG Node = 'fenpin:inst10\|enter\[22\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "6.961 ns" { clk fenpin:inst10|enter[22] } "NODE_NAME" } "" } } { "fenpin.vhd" "" { Text "D:/miaobiao/fenpin.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.523 ns) + CELL(0.590 ns) 9.543 ns rtl~426 3 COMB LC_X26_Y12_N9 1 " "Info: 3: + IC(0.523 ns) + CELL(0.590 ns) = 9.543 ns; Loc. = LC_X26_Y12_N9; Fanout = 1; COMB Node = 'rtl~426'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "1.113 ns" { fenpin:inst10|enter[22] rtl~426 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.402 ns) + CELL(0.590 ns) 11.535 ns rtl~428 4 COMB LC_X27_Y13_N2 1 " "Info: 4: + IC(1.402 ns) + CELL(0.590 ns) = 11.535 ns; Loc. = LC_X27_Y13_N2; Fanout = 1; COMB Node = 'rtl~428'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "1.992 ns" { rtl~426 rtl~428 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.443 ns) + CELL(0.292 ns) 12.270 ns rtl~6 5 COMB LC_X27_Y13_N8 12 " "Info: 5: + IC(0.443 ns) + CELL(0.292 ns) = 12.270 ns; Loc. = LC_X27_Y13_N8; Fanout = 12; COMB Node = 'rtl~6'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "0.735 ns" { rtl~428 rtl~6 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.405 ns) + CELL(0.935 ns) 18.610 ns msecond:inst\|ensec 6 REG LC_X11_Y21_N8 9 " "Info: 6: + IC(5.405 ns) + CELL(0.935 ns) = 18.610 ns; Loc. = LC_X11_Y21_N8; Fanout = 9; REG Node = 'msecond:inst\|ensec'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "6.340 ns" { rtl~6 msecond:inst|ensec } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "D:/miaobiao/msecond.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.910 ns) + CELL(0.711 ns) 24.231 ns second:inst5\|count\[4\] 7 REG LC_X11_Y20_N5 6 " "Info: 7: + IC(4.910 ns) + CELL(0.711 ns) = 24.231 ns; Loc. = LC_X11_Y20_N5; Fanout = 6; REG Node = 'second:inst5\|count\[4\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "5.621 ns" { msecond:inst|ensec second:inst5|count[4] } "NODE_NAME" } "" } } { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.522 ns ( 22.79 % ) " "Info: Total cell delay = 5.522 ns ( 22.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "18.709 ns ( 77.21 % ) " "Info: Total interconnect delay = 18.709 ns ( 77.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "24.231 ns" { clk fenpin:inst10|enter[22] rtl~426 rtl~428 rtl~6 msecond:inst|ensec second:inst5|count[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "24.231 ns" { clk clk~out0 fenpin:inst10|enter[22] rtl~426 rtl~428 rtl~6 msecond:inst|ensec second:inst5|count[4] } { 0.000ns 0.000ns 6.026ns 0.523ns 1.402ns 0.443ns 5.405ns 4.910ns } { 0.000ns 1.469ns 0.935ns 0.590ns 0.590ns 0.292ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "21.066 ns" { clk fenpin:inst10|enter[13] rtl~431 rtl~6 msecond:inst|ensec second:inst5|enmin } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "21.066 ns" { clk clk~out0 fenpin:inst10|enter[13] rtl~431 rtl~6 msecond:inst|ensec second:inst5|enmin } { 0.000ns 0.000ns 6.027ns 0.000ns 0.182ns 5.405ns 4.910ns } { 0.000ns 1.469ns 0.935ns 0.378ns 0.114ns 0.935ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "24.231 ns" { clk fenpin:inst10|enter[22] rtl~426 rtl~428 rtl~6 msecond:inst|ensec second:inst5|count[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "24.231 ns" { clk clk~out0 fenpin:inst10|enter[22] rtl~426 rtl~428 rtl~6 msecond:inst|ensec second:inst5|count[4] } { 0.000ns 0.000ns 6.026ns 0.523ns 1.402ns 0.443ns 5.405ns 4.910ns } { 0.000ns 1.469ns 0.935ns 0.590ns 0.590ns 0.292ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 7 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "4.748 ns" { second:inst5|count[4] second:inst5|enmin~201 second:inst5|enmin~202 second:inst5|enmin } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.748 ns" { second:inst5|count[4] second:inst5|enmin~201 second:inst5|enmin~202 second:inst5|enmin } { 0.000ns 1.261ns 1.236ns 1.107ns } { 0.000ns 0.114ns 0.292ns 0.738ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "21.066 ns" { clk fenpin:inst10|enter[13] rtl~431 rtl~6 msecond:inst|ensec second:inst5|enmin } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "21.066 ns" { clk clk~out0 fenpin:inst10|enter[13] rtl~431 rtl~6 msecond:inst|ensec second:inst5|enmin } { 0.000ns 0.000ns 6.027ns 0.000ns 0.182ns 5.405ns 4.910ns } { 0.000ns 1.469ns 0.935ns 0.378ns 0.114ns 0.935ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miba" "UNKNOWN" "V1" "D:/miaobiao/db/miba.quartus_db" { Floorplan "D:/miaobiao/" "" "24.231 ns" { clk fenpin:inst10|enter[22] rtl~426 rtl~428 rtl~6 msecond:inst|ensec second:inst5|count[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "24.231 ns" { clk clk~out0 fenpin:inst10|enter[22] rtl~426 rtl~428 rtl~6 msecond:inst|ensec second:inst5|count[4] } { 0.000ns 0.000ns 6.026ns 0.523ns 1.402ns 0.443ns 5.405ns 4.910ns } { 0.000ns 1.469ns 0.935ns 0.590ns 0.590ns 0.292ns 0.935ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}