fenpin.fit.qmsg

VHDL语言设计的秒表

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0 0 "Finished register packing" 0 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.30 0 1 0 " "Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 3 41 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  41 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 42 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  42 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 45 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  45 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 42 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  42 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.897 ns register register " "Info: Estimated most critical path is register to register delay of 4.897 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns enter\[6\] 1 REG LAB_X11_Y18 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X11_Y18; Fanout = 4; REG Node = 'enter\[6\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { enter[6] } "NODE_NAME" } "" } } { "fenpin.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/fenpin.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.191 ns) + CELL(0.575 ns) 1.766 ns add~613COUT1_646 2 COMB LAB_X11_Y16 2 " "Info: 2: + IC(1.191 ns) + CELL(0.575 ns) = 1.766 ns; Loc. = LAB_X11_Y16; Fanout = 2; COMB Node = 'add~613COUT1_646'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "1.766 ns" { enter[6] add~613COUT1_646 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.846 ns add~608COUT1_647 3 COMB LAB_X11_Y16 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.846 ns; Loc. = LAB_X11_Y16; Fanout = 2; COMB Node = 'add~608COUT1_647'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "0.080 ns" { add~613COUT1_646 add~608COUT1_647 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.926 ns add~588COUT1_648 4 COMB LAB_X11_Y16 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.926 ns; Loc. = LAB_X11_Y16; Fanout = 2; COMB Node = 'add~588COUT1_648'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "0.080 ns" { add~608COUT1_647 add~588COUT1_648 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 2.006 ns add~583COUT1_649 5 COMB LAB_X11_Y16 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 2.006 ns; Loc. = LAB_X11_Y16; Fanout = 2; COMB Node = 'add~583COUT1_649'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "0.080 ns" { add~588COUT1_648 add~583COUT1_649 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 2.264 ns add~578 6 COMB LAB_X11_Y16 6 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 2.264 ns; Loc. = LAB_X11_Y16; Fanout = 6; COMB Node = 'add~578'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "0.258 ns" { add~583COUT1_649 add~578 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.400 ns add~563 7 COMB LAB_X11_Y16 6 " "Info: 7: + IC(0.000 ns) + CELL(0.136 ns) = 2.400 ns; Loc. = LAB_X11_Y16; Fanout = 6; COMB Node = 'add~563'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "0.136 ns" { add~578 add~563 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.536 ns add~538 8 COMB LAB_X11_Y15 6 " "Info: 8: + IC(0.000 ns) + CELL(0.136 ns) = 2.536 ns; Loc. = LAB_X11_Y15; Fanout = 6; COMB Node = 'add~538'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "0.136 ns" { add~563 add~538 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.672 ns add~513 9 COMB LAB_X11_Y15 6 " "Info: 9: + IC(0.000 ns) + CELL(0.136 ns) = 2.672 ns; Loc. = LAB_X11_Y15; Fanout = 6; COMB Node = 'add~513'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "0.136 ns" { add~538 add~513 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.679 ns) 3.351 ns add~506 10 COMB LAB_X11_Y14 1 " "Info: 10: + IC(0.000 ns) + CELL(0.679 ns) = 3.351 ns; Loc. = LAB_X11_Y14; Fanout = 1; COMB Node = 'add~506'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "0.679 ns" { add~513 add~506 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.808 ns) + CELL(0.738 ns) 4.897 ns enter\[26\] 11 REG LAB_X10_Y17 4 " "Info: 11: + IC(0.808 ns) + CELL(0.738 ns) = 4.897 ns; Loc. = LAB_X10_Y17; Fanout = 4; REG Node = 'enter\[26\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "1.546 ns" { add~506 enter[26] } "NODE_NAME" } "" } } { "fenpin.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/fenpin.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.898 ns ( 59.18 % ) " "Info: Total cell delay = 2.898 ns ( 59.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.999 ns ( 40.82 % ) " "Info: Total interconnect delay = 1.999 ns ( 40.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "4.897 ns" { enter[6] add~613COUT1_646 add~608COUT1_647 add~588COUT1_648 add~583COUT1_649 add~578 add~563 add~538 add~513 add~506 enter[26] } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 11 00:43:16 2008 " "Info: Processing ended: Wed Jun 11 00:43:16 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}