fenpin.fit.rpt

VHDL语言设计的秒表

; Auto Global Clock                                    ; On                             ; On                             ;
; Auto Global Register Control Signals                 ; On                             ; On                             ;
+------------------------------------------------------+--------------------------------+--------------------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Active Serial            ;
; Error detection CRC                          ; Off                      ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in C:/Documents and Settings/Administrator/桌面/miaobiao/fenpin.fit.eqn.


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in C:/Documents and Settings/Administrator/桌面/miaobiao/fenpin.pin.


+---------------------------------------------------------------------+
; Fitter Resource Usage Summary                                       ;
+---------------------------------------------+-----------------------+
; Resource                                    ; Usage                 ;
+---------------------------------------------+-----------------------+
; Total logic elements                        ; 66 / 12,060 ( < 1 % ) ;
;     -- Combinational with no register       ; 34                    ;
;     -- Register only                        ; 20                    ;
;     -- Combinational with a register        ; 12                    ;
;                                             ;                       ;
; Logic element usage by number of LUT inputs ;                       ;
;     -- 4 input functions                    ; 10                    ;
;     -- 3 input functions                    ; 0                     ;
;     -- 2 input functions                    ; 35                    ;
;     -- 1 input functions                    ; 8                     ;
;     -- 0 input functions                    ; 13                    ;
;                                             ;                       ;
; Logic elements by mode                      ;                       ;
;     -- normal mode                          ; 35                    ;
;     -- arithmetic mode                      ; 31                    ;
;     -- qfbk mode                            ; 9                     ;
;     -- register cascade mode                ; 0                     ;
;     -- synchronous clear/load mode          ; 22                    ;
;     -- asynchronous clear/load mode         ; 0                     ;
;                                             ;                       ;
; Total LABs                                  ; 14 / 1,206 ( 1 % )    ;
; Logic elements in carry chains              ; 32                    ;
; User inserted logic elements                ; 0                     ;
; Virtual pins                                ; 0                     ;
; I/O pins                                    ; 2 / 173 ( 1 % )       ;
;     -- Clock pins                           ; 1 / 2 ( 50 % )        ;
; Global signals                              ; 1                     ;
; M4Ks                                        ; 0 / 52 ( 0 % )        ;
; Total memory bits                           ; 0 / 239,616 ( 0 % )   ;
; Total RAM block bits                        ; 0 / 239,616 ( 0 % )   ;
; PLLs                                        ; 0 / 2 ( 0 % )         ;
; Global clocks                               ; 1 / 8 ( 13 % )        ;
; Maximum fan-out node                        ; clk                   ;
; Maximum fan-out                             ; 32                    ;
; Highest non-global fan-out signal           ; add~513               ;
; Highest non-global fan-out                  ; 5                     ;
; Total fan-out                               ; 188                   ;
; Average fan-out                             ; 2.69                  ;
+---------------------------------------------+-----------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                 ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; clk  ; 29    ; 1        ; 0            ; 14           ; 0           ; 32                    ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; LVTTL        ; Off         ; Fitter               ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                                                     ;
+--------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------------+
; Name   ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load        ;
+--------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------------+
; newclk ; 23    ; 1        ; 0            ; 16           ; 0           ; no              ; no                     ; no            ; no             ; no              ; no         ; no            ; no       ; Off          ; LVTTL        ; 24mA             ; Off         ; Fitter               ; Unspecified ;
+--------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------------+


+----------------------------------------------------------+
; I/O Bank Usage                                           ;
+----------+----------------+---------------+--------------+
; I/O Bank ; Usage          ; VCCIO Voltage ; VREF Voltage ;
+----------+----------------+---------------+--------------+
; 1        ; 4 / 44 ( 9 % ) ; 3.3V          ; --           ;
; 2        ; 0 / 42 ( 0 % ) ; 3.3V          ; --           ;
; 3        ; 0 / 45 ( 0 % ) ; 3.3V          ; --           ;
; 4        ; 0 / 42 ( 0 % ) ; 3.3V          ; --           ;
+----------+----------------+---------------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; All Package Pins                                                                                                                                                        ;
+----------+------------+----------+-------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+