_primary.vhd

来自「这个是一个基于FPGA的数字图像的整数DCT变换程序」· VHDL 代码 · 共 19 行

library verilog;
use verilog.vl_types.all;
entity dct is
    port(
        clk             : in     vl_logic;
        rst_n           : in     vl_logic;
        data_in0        : in     vl_logic_vector(15 downto 0);
        data_in1        : in     vl_logic_vector(15 downto 0);
        data_in2        : in     vl_logic_vector(15 downto 0);
        data_in3        : in     vl_logic_vector(15 downto 0);
        data_out0       : out    vl_logic_vector(15 downto 0);
        data_out1       : out    vl_logic_vector(15 downto 0);
        data_out2       : out    vl_logic_vector(15 downto 0);
        data_out3       : out    vl_logic_vector(15 downto 0);
        data_in_en      : in     vl_logic;
        data_out_en     : out    vl_logic
    );
end dct;