traffic.tan.summary

来自「这个是用verilog语言编写的基于FPGA的交通灯控制器」· SUMMARY 代码 · 共 57 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 7.976 ns
From           : EN
To             : numa[5]
From Clock     : 
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 7.874 ns
From           : numa[3]
To             : ACOUNT[3]
From Clock     : CLK
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -4.715 ns
From           : EN
To             : counta.010
From Clock     : 
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 177.37 MHz ( period = 5.638 ns )
From           : numa[5]
To             : numa[4]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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