traffic.map.summary

这个是用verilog语言编写的基于FPGA的交通灯控制器

Flow Status : Successful - Mon Jun 02 15:37:07 2008
Quartus II Version : 5.0 Build 171 11/03/2005 SP 2 SJ Full Version
Revision Name : traffic
Top-level Entity Name : traffic
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 61
Total pins : 26
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0