traffic.map.rpt

来自「这个是用verilog语言编写的基于FPGA的交通灯控制器」· RPT 代码 · 共 306 行 · 第 1/2 页

+-----------------------------------------------------------------------------+
; State Machine - |traffic|counta                                             ;
+------------+------------+------------+------------+------------+------------+
; Name       ; counta.001 ; counta.010 ; counta.011 ; counta.000 ; counta.100 ;
+------------+------------+------------+------------+------------+------------+
; counta.000 ; 0          ; 0          ; 0          ; 0          ; 0          ;
; counta.011 ; 0          ; 0          ; 1          ; 1          ; 0          ;
; counta.010 ; 0          ; 1          ; 0          ; 1          ; 0          ;
; counta.001 ; 1          ; 0          ; 0          ; 1          ; 0          ;
; counta.100 ; 0          ; 0          ; 0          ; 1          ; 1          ;
+------------+------------+------------+------------+------------+------------+


+-----------------------------------------------------------------------------+
; State Machine - |traffic|countb                                             ;
+------------+------------+------------+------------+------------+------------+
; Name       ; countb.001 ; countb.010 ; countb.011 ; countb.000 ; countb.100 ;
+------------+------------+------------+------------+------------+------------+
; countb.000 ; 0          ; 0          ; 0          ; 0          ; 0          ;
; countb.011 ; 0          ; 0          ; 1          ; 1          ; 0          ;
; countb.010 ; 0          ; 1          ; 0          ; 1          ; 0          ;
; countb.001 ; 1          ; 0          ; 0          ; 1          ; 0          ;
; countb.100 ; 0          ; 0          ; 0          ; 1          ; 1          ;
+------------+------------+------------+------------+------------+------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 31    ;
; Number of registers using Synchronous Clear  ; 4     ;
; Number of registers using Synchronous Load   ; 10    ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 17    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |traffic|LAMPA[3]~reg0     ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |traffic|LAMPB[3]~reg0     ;
; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |traffic|numa[7]           ;
; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |traffic|numa[4]           ;
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |traffic|numa[0]           ;
; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |traffic|numb[5]           ;
; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |traffic|numb[4]           ;
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |traffic|numb[0]           ;
; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; No         ; |traffic|counta~5          ;
; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; No         ; |traffic|countb~5          ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/《FPGA系统设计与实战》初稿光盘/第3章_实战训练3,4,5/实战训练5 交通灯控制器/traffic.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
    Info: Processing started: Mon Jun 02 15:37:06 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off traffic -c traffic
Info: Found 1 design units, including 1 entities, in source file SRC/traffic.v
    Info: Found entity 1: traffic
Info: Elaborating entity "traffic" for the top level hierarchy
Warning: Verilog HDL Always Construct warning at traffic.v(14): variable "ared" may not be assigned a new value in every possible path through the Always Construct.  Variable "ared" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at traffic.v(14): variable "ayellow" may not be assigned a new value in every possible path through the Always Construct.  Variable "ayellow" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at traffic.v(14): variable "agreen" may not be assigned a new value in every possible path through the Always Construct.  Variable "agreen" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at traffic.v(14): variable "aleft" may not be assigned a new value in every possible path through the Always Construct.  Variable "aleft" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at traffic.v(14): variable "bred" may not be assigned a new value in every possible path through the Always Construct.  Variable "bred" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at traffic.v(14): variable "byellow" may not be assigned a new value in every possible path through the Always Construct.  Variable "byellow" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at traffic.v(14): variable "bleft" may not be assigned a new value in every possible path through the Always Construct.  Variable "bleft" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at traffic.v(14): variable "bgreen" may not be assigned a new value in every possible path through the Always Construct.  Variable "bgreen" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL assignment warning at traffic.v(33): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at traffic.v(37): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(42): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(47): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(52): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(57): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(61): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(68): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(71): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(73): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at traffic.v(79): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at traffic.v(87): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at traffic.v(91): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(96): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(101): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(106): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(111): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(115): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(121): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(122): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(125): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at traffic.v(127): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at traffic.v(132): truncated value with size 32 to match size of target (1)
Info: State machine "|traffic|counta" contains 5 states and 0 state bits
Info: State machine "|traffic|countb" contains 5 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|traffic|counta"
Info: Encoding result for state machine "|traffic|counta"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "counta.001"
        Info: Encoded state bit "counta.010"
        Info: Encoded state bit "counta.011"
        Info: Encoded state bit "counta.000"
        Info: Encoded state bit "counta.100"
    Info: State "|traffic|counta.000" uses code string "00000"
    Info: State "|traffic|counta.011" uses code string "00110"
    Info: State "|traffic|counta.010" uses code string "01010"
    Info: State "|traffic|counta.001" uses code string "10010"
    Info: State "|traffic|counta.100" uses code string "00011"
Info: Selected Auto state machine encoding method for state machine "|traffic|countb"
Info: Encoding result for state machine "|traffic|countb"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "countb.001"
        Info: Encoded state bit "countb.010"
        Info: Encoded state bit "countb.011"
        Info: Encoded state bit "countb.000"
        Info: Encoded state bit "countb.100"
    Info: State "|traffic|countb.000" uses code string "00000"
    Info: State "|traffic|countb.011" uses code string "00110"
    Info: State "|traffic|countb.010" uses code string "01010"
    Info: State "|traffic|countb.001" uses code string "10010"
    Info: State "|traffic|countb.100" uses code string "00011"
Info: Duplicate registers merged to single register
    Info: Duplicate register "counta.011" merged to single register "LAMPA[0]~reg0"
    Info: Duplicate register "counta.001" merged to single register "LAMPA[1]~reg0"
    Info: Duplicate register "counta.000" merged to single register "LAMPA[3]~reg0", power-up level changed
    Info: Duplicate register "countb.100" merged to single register "LAMPB[0]~reg0"
    Info: Duplicate register "countb.010" merged to single register "LAMPB[1]~reg0"
Info: Implemented 87 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 24 output pins
    Info: Implemented 61 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 31 warnings
    Info: Processing ended: Mon Jun 02 15:37:07 2008
    Info: Elapsed time: 00:00:01