traffic.sim.rpt

这个是用verilog语言编写的基于FPGA的交通灯控制器

Simulator report for traffic
Mon Jun 02 15:37:34 2008
Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Simulator Summary
  3. Simulator Settings
  4. Simulation Waveforms
  5. Simulator INI Usage
  6. Simulator Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+--------------------------------------------+
; Simulator Summary                          ;
+-----------------------------+--------------+
; Type                        ; Value        ;
+-----------------------------+--------------+
; Simulation Start Time       ; 0 ps         ;
; Simulation End Time         ; 1.0 us       ;
; Simulation Netlist Size     ; 375 nodes    ;
; Simulation Coverage         ;      11.69 % ;
; Total Number of Transitions ; 541          ;
+-----------------------------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Simulator Settings                                                                                                                               ;
+-------------------------------------------------------+------------------------------------------------------------------------------------------+
; Option                                                ; Setting                                                                                  ;
+-------------------------------------------------------+------------------------------------------------------------------------------------------+
; Simulation mode                                       ; Functional                                                                               ;
; Start time                                            ; 0ns                                                                                      ;
; Vector input source                                   ; D:/《FPGA系统设计与实战》初稿光盘/第3章_实战训练3,4,5/实战训练5 交通灯控制器/traffic.vwf ;
; Add pins automatically to simulation output waveforms ; On                                                                                       ;
; Check outputs                                         ; Off                                                                                      ;
; Report simulation coverage                            ; On                                                                                       ;
; Detect setup and hold time violations                 ; Off                                                                                      ;
; Detect glitches                                       ; Off                                                                                      ;
; Automatically save/load simulation netlist            ; Off                                                                                      ;
; Disable timing delays in Timing Simulation            ; Off                                                                                      ;
; Generate Signal Activity File                         ; On                                                                                       ;
; Signal Activity File output destination               ; D:/《FPGA系统设计与实战》初稿光盘/第3章_实战训练3,4,5/实战训练5 交通灯控制器/traffic.saf ;
; Glitch Filtering                                      ; On                                                                                       ;
+-------------------------------------------------------+------------------------------------------------------------------------------------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
    Info: Processing started: Mon Jun 02 15:37:34 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off traffic -c traffic
Info: Overwriting simulation input file with simulation results
Warning: Found clock-sensitive change during active clock edge at time 10.0 ns on register "|traffic|tempa"
Warning: Found clock-sensitive change during active clock edge at time 10.0 ns on register "|traffic|LAMPA[3]~reg0"
Warning: Found clock-sensitive change during active clock edge at time 10.0 ns on register "|traffic|LAMPA[1]~reg0"
Warning: Found clock-sensitive change during active clock edge at time 10.0 ns on register "|traffic|tempb"
Info: Simulation coverage is      11.69 %
Info: Number of transitions in simulation is 541
Info: Created Signal Activity File D:/《FPGA系统设计与实战》初稿光盘/第3章_实战训练3,4,5/实战训练5 交通灯控制器/traffic.saf
Info: Quartus II Simulator was successful. 0 errors, 4 warnings
    Info: Processing ended: Mon Jun 02 15:37:34 2008
    Info: Elapsed time: 00:00:00