test2.sta

This is my code (with PIC 18F458) for Modbus RTU Network. I have written by Ccs laguage

ROM used: 1590 (5%)
          1590 (5%) including unused fragments

          2 Average locations per line
          8 Average locations per statement

RAM used: 83 (5%) at main() level
          120 (8%) worst case

Stack used: 4 worst case (out of 29 total available)

Lines Stmts  %   Files
----- ----- ---  -----
  323   179  86  test2.c
  439     0   0  C:\Program Files\PICC\devices\18f4580.h
   45     0   0  board.h
  144    28  14  MODBUS-RTU.c
----- -----
  951   207 Total

Page ROM  %  RAM   Vol Diff  Functions:
---- --- --- ---   --- ----  ----------
0     46   1   4   131  4.2  response
0    130   4  17   822  8.8  getCRC
0     40   1   1             @delay_ms2
0    902  28   7  5630 11.9  receive
0     30   1   5             @MUL1616
0     32   1   0   152  1.8  setup
0    256   8   2   861  8.7  MAIN

Program metrics:
    Functions               5
    Statements              207
    Comments                195
    Volume (V)              9136
    Difficilty (D)          35.0
    Effort to implement (E) 319752
    Time to implement (T)   4 hours, 56 minutes
    Est Delivered Bugs (B)  2
    Cyclomatic Complexity   46
    Maintainability (MI)    57

 Segment     Used  Free
-----------  ----  ----
00000-00002     4  0  
00004-00006     0  4  
00008-0009C   150  0  
0009E-07FFE  1436  31174