alu.map.rpt

这是一个用vhdl语言实现的比较完整的ALU,可以用作其他cPU设计的部件

; I/O pins                          ; 32      ;
; Maximum fan-out node              ; b[2]    ;
; Maximum fan-out                   ; 46      ;
; Total fan-out                     ; 580     ;
; Average fan-out                   ; 3.01    ;
+-----------------------------------+---------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                             ;
+------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------------+
; Compilation Hierarchy Node         ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                              ;
+------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------------+
; |ALU                               ; 161 (150)   ; 0            ; 0           ; 32   ; 161 (150)    ; 0 (0)             ; 0 (0)            ; 11 (0)          ; |ALU                                                             ;
;    |lpm_add_sub:ALU_ADDER|         ; 11 (0)      ; 0            ; 0           ; 0    ; 11 (0)       ; 0 (0)             ; 0 (0)            ; 11 (0)          ; |ALU|lpm_add_sub:ALU_ADDER                                       ;
;       |addcore:adder|              ; 11 (1)      ; 0            ; 0           ; 0    ; 11 (1)       ; 0 (0)             ; 0 (0)            ; 11 (1)          ; |ALU|lpm_add_sub:ALU_ADDER|addcore:adder                         ;
;          |a_csnbuffer:result_node| ; 10 (10)     ; 0            ; 0           ; 0    ; 10 (10)      ; 0 (0)             ; 0 (0)            ; 10 (10)         ; |ALU|lpm_add_sub:ALU_ADDER|addcore:adder|a_csnbuffer:result_node ;
+------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |ALU ;
+----------------+-------+--------------------------------------------+
; Parameter Name ; Value ; Type                                       ;
+----------------+-------+--------------------------------------------+
; width          ; 7     ; Integer                                    ;
; op_w           ; 3     ; Integer                                    ;
+----------------+-------+--------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_add_sub:ALU_ADDER ;
+------------------------+-------------+-----------------------------+
; Parameter Name         ; Value       ; Type                        ;
+------------------------+-------------+-----------------------------+
; LPM_WIDTH              ; 8           ; Integer                     ;
; LPM_REPRESENTATION     ; SIGNED      ; Untyped                     ;
; LPM_DIRECTION          ; ADD         ; Untyped                     ;
; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                     ;
; LPM_PIPELINE           ; 0           ; Untyped                     ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                     ;
; REGISTERED_AT_END      ; 0           ; Untyped                     ;
; OPTIMIZE_FOR_SPEED     ; 1           ; Untyped                     ;
; USE_CS_BUFFERS         ; 1           ; Untyped                     ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                     ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH          ;
; DEVICE_FAMILY          ; ACEX1K      ; Untyped                     ;
; USE_WYS                ; OFF         ; Untyped                     ;
; STYLE                  ; FAST        ; Untyped                     ;
; CBXI_PARAMETER         ; add_sub_q0g ; Untyped                     ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                  ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE              ;
+------------------------+-------------+-----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in G:/组成实验/1.8 运算器部件实验：算术逻辑运算单元/alu.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Apr 10 23:14:09 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off alu -c alu
Info: Found 2 design units, including 1 entities, in source file ALU.VHD
    Info: Found design unit 1: ALU-struct
    Info: Found entity 1: ALU
Info: Elaborating entity "ALU" for the top level hierarchy
Info: VHDL Case Statement information at ALU.VHD(105): OTHERS choice is never selected
Info: VHDL Case Statement information at ALU.VHD(110): OTHERS choice is never selected
Info: VHDL Case Statement information at ALU.VHD(115): OTHERS choice is never selected
Info: VHDL Case Statement information at ALU.VHD(126): OTHERS choice is never selected
Info: VHDL Case Statement information at ALU.VHD(131): OTHERS choice is never selected
Info: VHDL Case Statement information at ALU.VHD(136): OTHERS choice is never selected
Info: VHDL Case Statement information at ALU.VHD(147): OTHERS choice is never selected
Info: VHDL Case Statement information at ALU.VHD(152): OTHERS choice is never selected
Info: VHDL Case Statement information at ALU.VHD(157): OTHERS choice is never selected
Info: VHDL Case Statement information at ALU.VHD(168): OTHERS choice is never selected
Info: VHDL Case Statement information at ALU.VHD(173): OTHERS choice is never selected
Info: VHDL Case Statement information at ALU.VHD(178): OTHERS choice is never selected
Info: VHDL Case Statement information at ALU.VHD(189): OTHERS choice is never selected
Info: VHDL Case Statement information at ALU.VHD(194): OTHERS choice is never selected
Info: VHDL Case Statement information at ALU.VHD(199): OTHERS choice is never selected
Info: VHDL Case Statement information at ALU.VHD(210): OTHERS choice is never selected
Info: VHDL Case Statement information at ALU.VHD(215): OTHERS choice is never selected
Info: VHDL Case Statement information at ALU.VHD(220): OTHERS choice is never selected
Info: VHDL Case Statement information at ALU.VHD(254): OTHERS choice is never selected
Info: Found 1 design units, including 1 entities, in source file ../../quartus50/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Elaborating entity "lpm_add_sub" for hierarchy "lpm_add_sub:ALU_ADDER"
Info: Found 1 design units, including 1 entities, in source file ../../quartus50/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Elaborating entity "addcore" for hierarchy "lpm_add_sub:ALU_ADDER|addcore:adder"
Info: Found 1 design units, including 1 entities, in source file ../../quartus50/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Elaborating entity "a_csnbuffer" for hierarchy "lpm_add_sub:ALU_ADDER|addcore:adder|a_csnbuffer:oflow_node"
Info: Elaborating entity "a_csnbuffer" for hierarchy "lpm_add_sub:ALU_ADDER|addcore:adder|a_csnbuffer:result_node"
Info: Found 1 design units, including 1 entities, in source file ../../quartus50/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Elaborating entity "altshift" for hierarchy "lpm_add_sub:ALU_ADDER|altshift:result_ext_latency_ffs"
Info: Elaborating entity "altshift" for hierarchy "lpm_add_sub:ALU_ADDER|altshift:carry_ext_latency_ffs"
Info: Ignored 2 buffer(s)
    Info: Ignored 2 SOFT buffer(s)
Info: Converted 1 single input CARRY primitives to CARRY_SUM primitives
Info: Implemented 193 device resources after synthesis - the final resource count might be different
    Info: Implemented 20 input pins
    Info: Implemented 12 output pins
    Info: Implemented 161 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Fri Apr 10 23:14:12 2009
    Info: Elapsed time: 00:00:03