alu.map.rpt

这是一个用vhdl语言实现的比较完整的ALU,可以用作其他cPU设计的部件

Analysis & Synthesis report for alu
Fri Apr 10 23:14:12 2009
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. General Register Statistics
  8. Parameter Settings for User Entity Instance: Top-level Entity: |ALU
  9. Parameter Settings for User Entity Instance: lpm_add_sub:ALU_ADDER
 10. Analysis & Synthesis Equations
 11. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Fri Apr 10 23:14:12 2009    ;
; Quartus II Version          ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name               ; alu                                      ;
; Top-level Entity Name       ; ALU                                      ;
; Family                      ; ACEX1K                                   ;
; Total logic elements        ; 161                                      ;
; Total pins                  ; 32                                       ;
; Total memory bits           ; 0                                        ;
; Total PLLs                  ; 0                                        ;
+-----------------------------+------------------------------------------+


+---------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                               ;
+------------------------------------------------------------+----------------+---------------+
; Option                                                     ; Setting        ; Default Value ;
+------------------------------------------------------------+----------------+---------------+
; Device                                                     ; EP1K100QC208-3 ;               ;
; Top-level entity name                                      ; ALU            ; alu           ;
; Family name                                                ; ACEX1K         ; Stratix       ;
; Use smart compilation                                      ; Off            ; Off           ;
; Create Debugging Nodes for IP Cores                        ; off            ; off           ;
; Preserve fewer node names                                  ; On             ; On            ;
; Disable OpenCore Plus hardware evaluation                  ; Off            ; Off           ;
; Verilog Version                                            ; Verilog_2001   ; Verilog_2001  ;
; VHDL Version                                               ; VHDL93         ; VHDL93        ;
; State Machine Processing                                   ; Auto           ; Auto          ;
; Extract Verilog State Machines                             ; On             ; On            ;
; Extract VHDL State Machines                                ; On             ; On            ;
; Add Pass-Through Logic to Inferred RAMs                    ; On             ; On            ;
; NOT Gate Push-Back                                         ; On             ; On            ;
; Power-Up Don't Care                                        ; On             ; On            ;
; Remove Redundant Logic Cells                               ; Off            ; Off           ;
; Remove Duplicate Registers                                 ; On             ; On            ;
; Ignore CARRY Buffers                                       ; Off            ; Off           ;
; Ignore CASCADE Buffers                                     ; Off            ; Off           ;
; Ignore GLOBAL Buffers                                      ; Off            ; Off           ;
; Ignore ROW GLOBAL Buffers                                  ; Off            ; Off           ;
; Ignore LCELL Buffers                                       ; Off            ; Off           ;
; Ignore SOFT Buffers                                        ; On             ; On            ;
; Limit AHDL Integers to 32 Bits                             ; Off            ; Off           ;
; Auto Implement in ROM                                      ; Off            ; Off           ;
; Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K       ; Area           ; Area          ;
; Carry Chain Length -- FLEX 10K                             ; 32             ; 32            ;
; Cascade Chain Length                                       ; 2              ; 2             ;
; Auto Carry Chains                                          ; On             ; On            ;
; Auto Open-Drain Pins                                       ; On             ; On            ;
; Remove Duplicate Logic                                     ; On             ; On            ;
; Auto ROM Replacement                                       ; On             ; On            ;
; Auto RAM Replacement                                       ; On             ; On            ;
; Auto Clock Enable Replacement                              ; On             ; On            ;
; Auto Resource Sharing                                      ; Off            ; Off           ;
; Allow Any RAM Size For Recognition                         ; Off            ; Off           ;
; Allow Any ROM Size For Recognition                         ; Off            ; Off           ;
; Ignore translate_off and translate_on Synthesis Directives ; Off            ; Off           ;
; Show Parameter Settings Tables in Synthesis Report         ; On             ; On            ;
+------------------------------------------------------------+----------------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                              ;
+----------------------------------+-----------------+-----------------+--------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                                 ;
+----------------------------------+-----------------+-----------------+--------------------------------------------------------------+
; ALU.VHD                          ; yes             ; User VHDL File  ; G:/组成实验/1.8 运算器部件实验：算术逻辑运算单元/ALU.VHD     ;
; lpm_add_sub.tdf                  ; yes             ; Megafunction    ; g:/quartus50/libraries/megafunctions/lpm_add_sub.tdf         ;
; addcore.inc                      ; yes             ; Other           ; g:/quartus50/libraries/megafunctions/addcore.inc             ;
; look_add.inc                     ; yes             ; Other           ; g:/quartus50/libraries/megafunctions/look_add.inc            ;
; bypassff.inc                     ; yes             ; Other           ; g:/quartus50/libraries/megafunctions/bypassff.inc            ;
; altshift.inc                     ; yes             ; Other           ; g:/quartus50/libraries/megafunctions/altshift.inc            ;
; alt_stratix_add_sub.inc          ; yes             ; Other           ; g:/quartus50/libraries/megafunctions/alt_stratix_add_sub.inc ;
; alt_mercury_add_sub.inc          ; yes             ; Other           ; g:/quartus50/libraries/megafunctions/alt_mercury_add_sub.inc ;
; aglobal50.inc                    ; yes             ; Other           ; g:/quartus50/libraries/megafunctions/aglobal50.inc           ;
; addcore.tdf                      ; yes             ; Megafunction    ; g:/quartus50/libraries/megafunctions/addcore.tdf             ;
; a_csnbuffer.inc                  ; yes             ; Other           ; g:/quartus50/libraries/megafunctions/a_csnbuffer.inc         ;
; a_csnbuffer.tdf                  ; yes             ; Megafunction    ; g:/quartus50/libraries/megafunctions/a_csnbuffer.tdf         ;
; altshift.tdf                     ; yes             ; Megafunction    ; g:/quartus50/libraries/megafunctions/altshift.tdf            ;
+----------------------------------+-----------------+-----------------+--------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Total logic elements              ; 161     ;
; Total combinational functions     ; 161     ;
;     -- Total 4-input functions    ; 90      ;
;     -- Total 3-input functions    ; 55      ;
;     -- Total 2-input functions    ; 14      ;
;     -- Total 1-input functions    ; 0       ;
;     -- Total 0-input functions    ; 2       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 0       ;
; Total logic cells in carry chains ; 11      ;