shifter.tan.qmsg

这是一个用vHDL语言实现的移位器

{ "Info" "ITDB_FULL_TCO_RESULT" "clock data_out\[7\] data_out\[7\]~reg0 14.900 ns register " "Info: tco from clock \"clock\" to destination pin \"data_out\[7\]\" through register \"data_out\[7\]~reg0\" is 14.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 1.900 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clock 1 CLK PIN_79 24 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 24; CLK Node = 'clock'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "" { clock } "NODE_NAME" } "" } } { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns data_out\[7\]~reg0 2 REG LC7_B2 1 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC7_B2; Fanout = 1; REG Node = 'data_out\[7\]~reg0'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "1.400 ns" { clock data_out[7]~reg0 } "NODE_NAME" } "" } } { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns 26.32 % " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 73.68 % " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "1.900 ns" { clock data_out[7]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out data_out[7]~reg0 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.900 ns + Longest register pin " "Info: + Longest register to pin delay is 11.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data_out\[7\]~reg0 1 REG LC7_B2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_B2; Fanout = 1; REG Node = 'data_out\[7\]~reg0'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "" { data_out[7]~reg0 } "NODE_NAME" } "" } } { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(8.600 ns) 11.900 ns data_out\[7\] 2 PIN PIN_15 0 " "Info: 2: + IC(3.300 ns) + CELL(8.600 ns) = 11.900 ns; Loc. = PIN_15; Fanout = 0; PIN Node = 'data_out\[7\]'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "11.900 ns" { data_out[7]~reg0 data_out[7] } "NODE_NAME" } "" } } { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.600 ns 72.27 % " "Info: Total cell delay = 8.600 ns ( 72.27 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns 27.73 % " "Info: Total interconnect delay = 3.300 ns ( 27.73 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "11.900 ns" { data_out[7]~reg0 data_out[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.900 ns" { data_out[7]~reg0 data_out[7] } { 0.000ns 3.300ns } { 0.000ns 8.600ns } } }  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "1.900 ns" { clock data_out[7]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out data_out[7]~reg0 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "11.900 ns" { data_out[7]~reg0 data_out[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.900 ns" { data_out[7]~reg0 data_out[7] } { 0.000ns 3.300ns } { 0.000ns 8.600ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "x\[4\] n\[0\] clock -7.100 ns register " "Info: th for register \"x\[4\]\" (data pin = \"n\[0\]\", clock pin = \"clock\") is -7.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 1.900 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clock 1 CLK PIN_79 24 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 24; CLK Node = 'clock'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "" { clock } "NODE_NAME" } "" } } { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns x\[4\] 2 REG LC4_B22 2 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC4_B22; Fanout = 2; REG Node = 'x\[4\]'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "1.400 ns" { clock x[4] } "NODE_NAME" } "" } } { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns 26.32 % " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 73.68 % " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "1.900 ns" { clock x[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out x[4] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.900 ns + " "Info: + Micro hold delay of destination is 0.900 ns" {  } { { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.900 ns - Shortest pin register " "Info: - Shortest pin to register delay is 9.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns n\[0\] 1 PIN PIN_58 24 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_58; Fanout = 24; PIN Node = 'n\[0\]'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "" { n[0] } "NODE_NAME" } "" } } { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.600 ns) + CELL(1.200 ns) 9.900 ns x\[4\] 2 REG LC4_B22 2 " "Info: 2: + IC(5.600 ns) + CELL(1.200 ns) = 9.900 ns; Loc. = LC4_B22; Fanout = 2; REG Node = 'x\[4\]'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "6.800 ns" { n[0] x[4] } "NODE_NAME" } "" } } { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.300 ns 43.43 % " "Info: Total cell delay = 4.300 ns ( 43.43 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.600 ns 56.57 % " "Info: Total interconnect delay = 5.600 ns ( 56.57 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "9.900 ns" { n[0] x[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.900 ns" { n[0] n[0]~out x[4] } { 0.000ns 0.000ns 5.600ns } { 0.000ns 3.100ns 1.200ns } } }  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "1.900 ns" { clock x[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out x[4] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "9.900 ns" { n[0] x[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.900 ns" { n[0] n[0]~out x[4] } { 0.000ns 0.000ns 5.600ns } { 0.000ns 3.100ns 1.200ns } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clock data_out\[4\] data_out\[4\]~reg0 13.100 ns register " "Info: Minimum tco from clock \"clock\" to destination pin \"data_out\[4\]\" through register \"data_out\[4\]~reg0\" is 13.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 1.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clock 1 CLK PIN_79 24 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 24; CLK Node = 'clock'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "" { clock } "NODE_NAME" } "" } } { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns data_out\[4\]~reg0 2 REG LC4_B4 1 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC4_B4; Fanout = 1; REG Node = 'data_out\[4\]~reg0'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "1.400 ns" { clock data_out[4]~reg0 } "NODE_NAME" } "" } } { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns 26.32 % " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 73.68 % " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "1.900 ns" { clock data_out[4]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out data_out[4]~reg0 } { 0.0ns 0.0ns 1.4ns } { 0.0ns 0.5ns 0.0ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.100 ns + Shortest register pin " "Info: + Shortest register to pin delay is 10.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data_out\[4\]~reg0 1 REG LC4_B4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_B4; Fanout = 1; REG Node = 'data_out\[4\]~reg0'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "" { data_out[4]~reg0 } "NODE_NAME" } "" } } { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(8.600 ns) 10.100 ns data_out\[4\] 2 PIN PIN_12 0 " "Info: 2: + IC(1.500 ns) + CELL(8.600 ns) = 10.100 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'data_out\[4\]'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "10.100 ns" { data_out[4]~reg0 data_out[4] } "NODE_NAME" } "" } } { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.600 ns 85.15 % " "Info: Total cell delay = 8.600 ns ( 85.15 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns 14.85 % " "Info: Total interconnect delay = 1.500 ns ( 14.85 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "10.100 ns" { data_out[4]~reg0 data_out[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.100 ns" { data_out[4]~reg0 data_out[4] } { 0.0ns 1.5ns } { 0.0ns 8.6ns } } }  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "1.900 ns" { clock data_out[4]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out data_out[4]~reg0 } { 0.0ns 0.0ns 1.4ns } { 0.0ns 0.5ns 0.0ns } } } { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "10.100 ns" { data_out[4]~reg0 data_out[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.100 ns" { data_out[4]~reg0 data_out[4] } { 0.0ns 1.5ns } { 0.0ns 8.6ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 23 16:22:08 2005 " "Info: Processing ended: Tue Aug 23 16:22:08 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}