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📄 shifter.tan.qmsg

📁 这是一个用vHDL语言实现的移位器
💻 QMSG
📖 第 1 页 / 共 4 页
字号:
🔍
1234 
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" {  } { { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register x\[7\] register data_out\[6\]~reg0 44.84 MHz 22.3 ns Internal " "Info: Clock \"clock\" has Internal fmax of 44.84 MHz between source register \"x\[7\]\" and destination register \"data_out\[6\]~reg0\" (period= 22.3 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "20.500 ns + Longest register register " "Info: + Longest register to register delay is 20.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns x\[7\] 1 REG LC1_B7 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B7; Fanout = 2; REG Node = 'x\[7\]'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "" { x[7] } "NODE_NAME" } "" } } { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.700 ns) 2.800 ns Mux~2104 2 COMB LC8_B8 1 " "Info: 2: + IC(1.100 ns) + CELL(1.700 ns) = 2.800 ns; Loc. = LC8_B8; Fanout = 1; COMB Node = 'Mux~2104'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "2.800 ns" { x[7] Mux~2104 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.900 ns) 4.900 ns Mux~2105 3 COMB LC3_B8 2 " "Info: 3: + IC(0.200 ns) + CELL(1.900 ns) = 4.900 ns; Loc. = LC3_B8; Fanout = 2; COMB Node = 'Mux~2105'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "2.100 ns" { Mux~2104 Mux~2105 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 7.100 ns Mux~2108 4 COMB LC1_B8 7 " "Info: 4: + IC(0.200 ns) + CELL(2.000 ns) = 7.100 ns; Loc. = LC1_B8; Fanout = 7; COMB Node = 'Mux~2108'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "2.200 ns" { Mux~2105 Mux~2108 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.900 ns) 10.100 ns Mux~2154 5 COMB LC5_B5 1 " "Info: 5: + IC(1.100 ns) + CELL(1.900 ns) = 10.100 ns; Loc. = LC5_B5; Fanout = 1; COMB Node = 'Mux~2154'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "3.000 ns" { Mux~2108 Mux~2154 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.900 ns) 12.200 ns Mux~2155 6 COMB LC6_B5 2 " "Info: 6: + IC(0.200 ns) + CELL(1.900 ns) = 12.200 ns; Loc. = LC6_B5; Fanout = 2; COMB Node = 'Mux~2155'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "2.100 ns" { Mux~2154 Mux~2155 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 14.400 ns Mux~2158 7 COMB LC1_B5 3 " "Info: 7: + IC(0.200 ns) + CELL(2.000 ns) = 14.400 ns; Loc. = LC1_B5; Fanout = 3; COMB Node = 'Mux~2158'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "2.200 ns" { Mux~2155 Mux~2158 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.700 ns) 17.200 ns Mux~2167 8 COMB LC2_B4 3 " "Info: 8: + IC(1.100 ns) + CELL(1.700 ns) = 17.200 ns; Loc. = LC2_B4; Fanout = 3; COMB Node = 'Mux~2167'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "2.800 ns" { Mux~2158 Mux~2167 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 19.100 ns Mux~2171 9 COMB LC7_B4 1 " "Info: 9: + IC(0.200 ns) + CELL(1.700 ns) = 19.100 ns; Loc. = LC7_B4; Fanout = 1; COMB Node = 'Mux~2171'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "1.900 ns" { Mux~2167 Mux~2171 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.200 ns) 20.500 ns data_out\[6\]~reg0 10 REG LC3_B4 1 " "Info: 10: + IC(0.200 ns) + CELL(1.200 ns) = 20.500 ns; Loc. = LC3_B4; Fanout = 1; REG Node = 'data_out\[6\]~reg0'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "1.400 ns" { Mux~2171 data_out[6]~reg0 } "NODE_NAME" } "" } } { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "16.000 ns 78.05 % " "Info: Total cell delay = 16.000 ns ( 78.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.500 ns 21.95 % " "Info: Total interconnect delay = 4.500 ns ( 21.95 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "20.500 ns" { x[7] Mux~2104 Mux~2105 Mux~2108 Mux~2154 Mux~2155 Mux~2158 Mux~2167 Mux~2171 data_out[6]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "20.500 ns" { x[7] Mux~2104 Mux~2105 Mux~2108 Mux~2154 Mux~2155 Mux~2158 Mux~2167 Mux~2171 data_out[6]~reg0 } { 0.000ns 1.100ns 0.200ns 0.200ns 1.100ns 0.200ns 0.200ns 1.100ns 0.200ns 0.200ns } { 0.000ns 1.700ns 1.900ns 2.000ns 1.900ns 1.900ns 2.000ns 1.700ns 1.700ns 1.200ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 1.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clock 1 CLK PIN_79 24 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 24; CLK Node = 'clock'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "" { clock } "NODE_NAME" } "" } } { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns data_out\[6\]~reg0 2 REG LC3_B4 1 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC3_B4; Fanout = 1; REG Node = 'data_out\[6\]~reg0'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "1.400 ns" { clock data_out[6]~reg0 } "NODE_NAME" } "" } } { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns 26.32 % " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 73.68 % " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "1.900 ns" { clock data_out[6]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out data_out[6]~reg0 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 1.900 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clock 1 CLK PIN_79 24 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 24; CLK Node = 'clock'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "" { clock } "NODE_NAME" } "" } } { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns x\[7\] 2 REG LC1_B7 2 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_B7; Fanout = 2; REG Node = 'x\[7\]'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "1.400 ns" { clock x[7] } "NODE_NAME" } "" } } { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns 26.32 % " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 73.68 % " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "1.900 ns" { clock x[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out x[7] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "1.900 ns" { clock data_out[6]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out data_out[6]~reg0 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "1.900 ns" { clock x[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out x[7] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 24 -1 0 } }  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "20.500 ns" { x[7] Mux~2104 Mux~2105 Mux~2108 Mux~2154 Mux~2155 Mux~2158 Mux~2167 Mux~2171 data_out[6]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "20.500 ns" { x[7] Mux~2104 Mux~2105 Mux~2108 Mux~2154 Mux~2155 Mux~2158 Mux~2167 Mux~2171 data_out[6]~reg0 } { 0.000ns 1.100ns 0.200ns 0.200ns 1.100ns 0.200ns 0.200ns 1.100ns 0.200ns 0.200ns } { 0.000ns 1.700ns 1.900ns 2.000ns 1.900ns 1.900ns 2.000ns 1.700ns 1.700ns 1.200ns } } } { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "1.900 ns" { clock data_out[6]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out data_out[6]~reg0 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "1.900 ns" { clock x[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out x[7] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "data_out\[4\]~reg0 dir clock 31.000 ns register " "Info: tsu for register \"data_out\[4\]~reg0\" (data pin = \"dir\", clock pin = \"clock\") is 31.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "32.200 ns + Longest pin register " "Info: + Longest pin to register delay is 32.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns dir 1 PIN PIN_57 36 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_57; Fanout = 36; PIN Node = 'dir'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "" { dir } "NODE_NAME" } "" } } { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.500 ns) + CELL(2.000 ns) 11.600 ns Mux~2106 2 COMB LC2_B22 1 " "Info: 2: + IC(6.500 ns) + CELL(2.000 ns) = 11.600 ns; Loc. = LC2_B22; Fanout = 1; COMB Node = 'Mux~2106'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "8.500 ns" { dir Mux~2106 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(1.900 ns) 15.500 ns Mux~2107 3 COMB LC2_B7 2 " "Info: 3: + IC(2.000 ns) + CELL(1.900 ns) = 15.500 ns; Loc. = LC2_B7; Fanout = 2; COMB Node = 'Mux~2107'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "3.900 ns" { Mux~2106 Mux~2107 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.200 ns) 18.800 ns Mux~2108 4 COMB LC1_B8 7 " "Info: 4: + IC(1.100 ns) + CELL(2.200 ns) = 18.800 ns; Loc. = LC1_B8; Fanout = 7; COMB Node = 'Mux~2108'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "3.300 ns" { Mux~2107 Mux~2108 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.900 ns) 21.800 ns Mux~2154 5 COMB LC5_B5 1 " "Info: 5: + IC(1.100 ns) + CELL(1.900 ns) = 21.800 ns; Loc. = LC5_B5; Fanout = 1; COMB Node = 'Mux~2154'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "3.000 ns" { Mux~2108 Mux~2154 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.900 ns) 23.900 ns Mux~2155 6 COMB LC6_B5 2 " "Info: 6: + IC(0.200 ns) + CELL(1.900 ns) = 23.900 ns; Loc. = LC6_B5; Fanout = 2; COMB Node = 'Mux~2155'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "2.100 ns" { Mux~2154 Mux~2155 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 26.100 ns Mux~2158 7 COMB LC1_B5 3 " "Info: 7: + IC(0.200 ns) + CELL(2.000 ns) = 26.100 ns; Loc. = LC1_B5; Fanout = 3; COMB Node = 'Mux~2158'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "2.200 ns" { Mux~2155 Mux~2158 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.700 ns) 28.900 ns Mux~2167 8 COMB LC2_B4 3 " "Info: 8: + IC(1.100 ns) + CELL(1.700 ns) = 28.900 ns; Loc. = LC2_B4; Fanout = 3; COMB Node = 'Mux~2167'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "2.800 ns" { Mux~2158 Mux~2167 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 30.800 ns Mux~2169 9 COMB LC5_B4 1 " "Info: 9: + IC(0.200 ns) + CELL(1.700 ns) = 30.800 ns; Loc. = LC5_B4; Fanout = 1; COMB Node = 'Mux~2169'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "1.900 ns" { Mux~2167 Mux~2169 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.200 ns) 32.200 ns data_out\[4\]~reg0 10 REG LC4_B4 1 " "Info: 10: + IC(0.200 ns) + CELL(1.200 ns) = 32.200 ns; Loc. = LC4_B4; Fanout = 1; REG Node = 'data_out\[4\]~reg0'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "1.400 ns" { Mux~2169 data_out[4]~reg0 } "NODE_NAME" } "" } } { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "19.600 ns 60.87 % " "Info: Total cell delay = 19.600 ns ( 60.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.600 ns 39.13 % " "Info: Total interconnect delay = 12.600 ns ( 39.13 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "32.200 ns" { dir Mux~2106 Mux~2107 Mux~2108 Mux~2154 Mux~2155 Mux~2158 Mux~2167 Mux~2169 data_out[4]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "32.200 ns" { dir dir~out Mux~2106 Mux~2107 Mux~2108 Mux~2154 Mux~2155 Mux~2158 Mux~2167 Mux~2169 data_out[4]~reg0 } { 0.000ns 0.000ns 6.500ns 2.000ns 1.100ns 1.100ns 0.200ns 0.200ns 1.100ns 0.200ns 0.200ns } { 0.000ns 3.100ns 2.000ns 1.900ns 2.200ns 1.900ns 1.900ns 2.000ns 1.700ns 1.700ns 1.200ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 1.900 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clock 1 CLK PIN_79 24 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 24; CLK Node = 'clock'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "" { clock } "NODE_NAME" } "" } } { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns data_out\[4\]~reg0 2 REG LC4_B4 1 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC4_B4; Fanout = 1; REG Node = 'data_out\[4\]~reg0'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "1.400 ns" { clock data_out[4]~reg0 } "NODE_NAME" } "" } } { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns 26.32 % " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 73.68 % " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "1.900 ns" { clock data_out[4]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out data_out[4]~reg0 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "32.200 ns" { dir Mux~2106 Mux~2107 Mux~2108 Mux~2154 Mux~2155 Mux~2158 Mux~2167 Mux~2169 data_out[4]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "32.200 ns" { dir dir~out Mux~2106 Mux~2107 Mux~2108 Mux~2154 Mux~2155 Mux~2158 Mux~2167 Mux~2169 data_out[4]~reg0 } { 0.000ns 0.000ns 6.500ns 2.000ns 1.100ns 1.100ns 0.200ns 0.200ns 1.100ns 0.200ns 0.200ns } { 0.000ns 3.100ns 2.000ns 1.900ns 2.200ns 1.900ns 1.900ns 2.000ns 1.700ns 1.700ns 1.200ns } } } { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/db/shifter.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/" "" "1.900 ns" { clock data_out[4]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out data_out[4]~reg0 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0}
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