shifter.map.qmsg

这是一个用vHDL语言实现的移位器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 23 16:21:43 2005 " "Info: Processing started: Tue Aug 23 16:21:43 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off shifter -c shifter " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shifter -c shifter" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file shifter.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 shifter-behav " "Info: Found design unit 1: shifter-behav" {  } { { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 18 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 shifter " "Info: Found entity 1: shifter" {  } { { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 7 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "shifter " "Info: Elaborating entity \"shifter\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clock shifter.vhd(24) " "Warning: VHDL Process Statement warning at shifter.vhd(24): signal \"clock\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "shifter.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/4-shifter/shifter.vhd" 24 0 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "158 " "Info: Implemented 158 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "15 " "Info: Implemented 15 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "135 " "Info: Implemented 135 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 23 16:21:46 2005 " "Info: Processing ended: Tue Aug 23 16:21:46 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}