adder8.tan.qmsg

实现十六位加法器

{ "Info" "ITDB_FULL_TPD_RESULT" "cin cout 42.900 ns Longest " "Info: Longest tpd from source pin \"cin\" to destination pin \"cout\" is 42.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns cin 1 PIN PIN_93 2 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_93; Fanout = 2; PIN Node = 'cin'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/" "" "" { cin } "NODE_NAME" } "" } } { "adder8.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/adder8.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.100 ns) + CELL(1.900 ns) 10.100 ns fulladder:f0\|CarryOut~53 2 COMB LC2_A52 2 " "Info: 2: + IC(5.100 ns) + CELL(1.900 ns) = 10.100 ns; Loc. = LC2_A52; Fanout = 2; COMB Node = 'fulladder:f0\|CarryOut~53'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/" "" "7.000 ns" { cin fulladder:f0|CarryOut~53 } "NODE_NAME" } "" } } { "fulladder.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/fulladder.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.700 ns) 13.600 ns fulladder:f1\|CarryOut~117 3 COMB LC3_A49 2 " "Info: 3: + IC(1.800 ns) + CELL(1.700 ns) = 13.600 ns; Loc. = LC3_A49; Fanout = 2; COMB Node = 'fulladder:f1\|CarryOut~117'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/" "" "3.500 ns" { fulladder:f0|CarryOut~53 fulladder:f1|CarryOut~117 } "NODE_NAME" } "" } } { "fulladder.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/fulladder.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 15.500 ns fulladder:f2\|CarryOut~171 4 COMB LC5_A49 2 " "Info: 4: + IC(0.200 ns) + CELL(1.700 ns) = 15.500 ns; Loc. = LC5_A49; Fanout = 2; COMB Node = 'fulladder:f2\|CarryOut~171'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/" "" "1.900 ns" { fulladder:f1|CarryOut~117 fulladder:f2|CarryOut~171 } "NODE_NAME" } "" } } { "fulladder.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/fulladder.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 17.400 ns fulladder:f3\|CarryOut~53 5 COMB LC2_A49 2 " "Info: 5: + IC(0.200 ns) + CELL(1.700 ns) = 17.400 ns; Loc. = LC2_A49; Fanout = 2; COMB Node = 'fulladder:f3\|CarryOut~53'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/" "" "1.900 ns" { fulladder:f2|CarryOut~171 fulladder:f3|CarryOut~53 } "NODE_NAME" } "" } } { "fulladder.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/fulladder.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.600 ns) + CELL(1.700 ns) 22.700 ns fulladder:f4\|CarryOut~53 6 COMB LC2_B44 2 " "Info: 6: + IC(3.600 ns) + CELL(1.700 ns) = 22.700 ns; Loc. = LC2_B44; Fanout = 2; COMB Node = 'fulladder:f4\|CarryOut~53'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/" "" "5.300 ns" { fulladder:f3|CarryOut~53 fulladder:f4|CarryOut~53 } "NODE_NAME" } "" } } { "fulladder.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/fulladder.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 24.600 ns fulladder:f5\|CarryOut~53 7 COMB LC4_B44 2 " "Info: 7: + IC(0.200 ns) + CELL(1.700 ns) = 24.600 ns; Loc. = LC4_B44; Fanout = 2; COMB Node = 'fulladder:f5\|CarryOut~53'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/" "" "1.900 ns" { fulladder:f4|CarryOut~53 fulladder:f5|CarryOut~53 } "NODE_NAME" } "" } } { "fulladder.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/fulladder.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 26.500 ns fulladder:f6\|CarryOut~53 8 COMB LC1_B44 2 " "Info: 8: + IC(0.200 ns) + CELL(1.700 ns) = 26.500 ns; Loc. = LC1_B44; Fanout = 2; COMB Node = 'fulladder:f6\|CarryOut~53'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/" "" "1.900 ns" { fulladder:f5|CarryOut~53 fulladder:f6|CarryOut~53 } "NODE_NAME" } "" } } { "fulladder.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/fulladder.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.600 ns) + CELL(1.700 ns) 31.800 ns fulladder:f7\|CarryOut~51 9 COMB LC4_C50 1 " "Info: 9: + IC(3.600 ns) + CELL(1.700 ns) = 31.800 ns; Loc. = LC4_C50; Fanout = 1; COMB Node = 'fulladder:f7\|CarryOut~51'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/" "" "5.300 ns" { fulladder:f6|CarryOut~53 fulladder:f7|CarryOut~51 } "NODE_NAME" } "" } } { "fulladder.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/fulladder.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(8.600 ns) 42.900 ns cout 10 PIN PIN_17 0 " "Info: 10: + IC(2.500 ns) + CELL(8.600 ns) = 42.900 ns; Loc. = PIN_17; Fanout = 0; PIN Node = 'cout'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/" "" "11.100 ns" { fulladder:f7|CarryOut~51 cout } "NODE_NAME" } "" } } { "adder8.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/adder8.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns 59.44 % " "Info: Total cell delay = 25.500 ns ( 59.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "17.400 ns 40.56 % " "Info: Total interconnect delay = 17.400 ns ( 40.56 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/" "" "42.900 ns" { cin fulladder:f0|CarryOut~53 fulladder:f1|CarryOut~117 fulladder:f2|CarryOut~171 fulladder:f3|CarryOut~53 fulladder:f4|CarryOut~53 fulladder:f5|CarryOut~53 fulladder:f6|CarryOut~53 fulladder:f7|CarryOut~51 cout } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "42.900 ns" { cin cin~out fulladder:f0|CarryOut~53 fulladder:f1|CarryOut~117 fulladder:f2|CarryOut~171 fulladder:f3|CarryOut~53 fulladder:f4|CarryOut~53 fulladder:f5|CarryOut~53 fulladder:f6|CarryOut~53 fulladder:f7|CarryOut~51 cout } { 0.000ns 0.000ns 5.100ns 1.800ns 0.200ns 0.200ns 3.600ns 0.200ns 0.200ns 3.600ns 2.500ns } { 0.000ns 3.100ns 1.900ns 1.700ns 1.700ns 1.700ns 1.700ns 1.700ns 1.700ns 1.700ns 8.600ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "b\[4\] sum\[4\] 18.200 ns Shortest " "Info: Shortest tpd from source pin \"b\[4\]\" to destination pin \"sum\[4\]\" is 18.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns b\[4\] 1 PIN PIN_57 2 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_57; Fanout = 2; PIN Node = 'b\[4\]'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/" "" "" { b[4] } "NODE_NAME" } "" } } { "adder8.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/adder8.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.000 ns) + CELL(1.700 ns) 8.800 ns fulladder:f4\|Sum 2 COMB LC4_B39 1 " "Info: 2: + IC(4.000 ns) + CELL(1.700 ns) = 8.800 ns; Loc. = LC4_B39; Fanout = 1; COMB Node = 'fulladder:f4\|Sum'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/" "" "5.700 ns" { b[4] fulladder:f4|Sum } "NODE_NAME" } "" } } { "fulladder.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/fulladder.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(8.600 ns) 18.200 ns sum\[4\] 3 PIN PIN_12 0 " "Info: 3: + IC(0.800 ns) + CELL(8.600 ns) = 18.200 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'sum\[4\]'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/" "" "9.400 ns" { fulladder:f4|Sum sum[4] } "NODE_NAME" } "" } } { "adder8.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/adder8.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.400 ns 73.63 % " "Info: Total cell delay = 13.400 ns ( 73.63 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.800 ns 26.37 % " "Info: Total interconnect delay = 4.800 ns ( 26.37 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/db/adder8.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/" "" "18.200 ns" { b[4] fulladder:f4|Sum sum[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "18.200 ns" { b[4] b[4]~out fulladder:f4|Sum sum[4] } { 0.0ns 0.0ns 4.0ns 0.8ns } { 0.0ns 3.1ns 1.7ns 8.6ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 07 10:42:27 2005 " "Info: Processing ended: Wed Sep 07 10:42:27 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}