📄 adder8.fit.eqn
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
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-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--B1L1 is fulladder:f0|CarryOut~53 at LC2_A52
--operation mode is normal
B1L1 = b[0] & (cin # a[0]) # !b[0] & cin & a[0];
--B1L2 is fulladder:f0|CarryOut~54 at LC2_A52
--operation mode is normal
B1L2 = b[0] & (cin # a[0]) # !b[0] & cin & a[0];
--B2L1 is fulladder:f1|CarryOut~117 at LC3_A49
--operation mode is normal
B2L1 = a[1] & (b[1] # B1L1) # !a[1] & b[1] & B1L1;
--B2L2 is fulladder:f1|CarryOut~118 at LC3_A49
--operation mode is normal
B2L2 = a[1] & (b[1] # B1L1) # !a[1] & b[1] & B1L1;
--B3L1 is fulladder:f2|CarryOut~171 at LC5_A49
--operation mode is normal
B3L1 = a[2] & (b[2] # B2L1) # !a[2] & b[2] & B2L1;
--B3L2 is fulladder:f2|CarryOut~172 at LC5_A49
--operation mode is normal
B3L2 = a[2] & (b[2] # B2L1) # !a[2] & b[2] & B2L1;
--B4L1 is fulladder:f3|CarryOut~53 at LC2_A49
--operation mode is normal
B4L1 = a[3] & (b[3] # B3L1) # !a[3] & b[3] & B3L1;
--B4L2 is fulladder:f3|CarryOut~54 at LC2_A49
--operation mode is normal
B4L2 = a[3] & (b[3] # B3L1) # !a[3] & b[3] & B3L1;
--B5L1 is fulladder:f4|CarryOut~53 at LC2_B44
--operation mode is normal
B5L1 = a[4] & (b[4] # B4L1) # !a[4] & b[4] & B4L1;
--B5L2 is fulladder:f4|CarryOut~54 at LC2_B44
--operation mode is normal
B5L2 = a[4] & (b[4] # B4L1) # !a[4] & b[4] & B4L1;
--B6L1 is fulladder:f5|CarryOut~53 at LC4_B44
--operation mode is normal
B6L1 = a[5] & (b[5] # B5L1) # !a[5] & b[5] & B5L1;
--B6L2 is fulladder:f5|CarryOut~54 at LC4_B44
--operation mode is normal
B6L2 = a[5] & (b[5] # B5L1) # !a[5] & b[5] & B5L1;
--B7L1 is fulladder:f6|CarryOut~53 at LC1_B44
--operation mode is normal
B7L1 = a[6] & (b[6] # B6L1) # !a[6] & b[6] & B6L1;
--B7L2 is fulladder:f6|CarryOut~54 at LC1_B44
--operation mode is normal
B7L2 = a[6] & (b[6] # B6L1) # !a[6] & b[6] & B6L1;
--B8L1 is fulladder:f7|CarryOut~51 at LC4_C50
--operation mode is normal
B8L1 = a[7] & (b[7] # B7L1) # !a[7] & b[7] & B7L1;
--B8L2 is fulladder:f7|CarryOut~52 at LC4_C50
--operation mode is normal
B8L2 = a[7] & (b[7] # B7L1) # !a[7] & b[7] & B7L1;
--B1L3 is fulladder:f0|Sum~15 at LC1_A52
--operation mode is normal
B1L3 = b[0] $ cin $ a[0];
--B1L4 is fulladder:f0|Sum~16 at LC1_A52
--operation mode is normal
B1L4 = b[0] $ cin $ a[0];
--B2_Sum is fulladder:f1|Sum at LC2_A30
--operation mode is normal
B2_Sum = b[1] $ a[1] $ B1L1;
--B2L4 is fulladder:f1|Sum~72 at LC2_A30
--operation mode is normal
B2L4 = b[1] $ a[1] $ B1L1;
--B3_Sum is fulladder:f2|Sum at LC4_A49
--operation mode is normal
B3_Sum = B2L1 $ a[2] $ b[2];
--B3L4 is fulladder:f2|Sum~10 at LC4_A49
--operation mode is normal
B3L4 = B2L1 $ a[2] $ b[2];
--B4_Sum is fulladder:f3|Sum at LC1_A49
--operation mode is normal
B4_Sum = B3L1 $ a[3] $ b[3];
--B4L4 is fulladder:f3|Sum~10 at LC1_A49
--operation mode is normal
B4L4 = B3L1 $ a[3] $ b[3];
--B5_Sum is fulladder:f4|Sum at LC4_B39
--operation mode is normal
B5_Sum = B4L1 $ a[4] $ b[4];
--B5L4 is fulladder:f4|Sum~10 at LC4_B39
--operation mode is normal
B5L4 = B4L1 $ a[4] $ b[4];
--B6_Sum is fulladder:f5|Sum at LC8_B44
--operation mode is normal
B6_Sum = B5L1 $ a[5] $ b[5];
--B6L4 is fulladder:f5|Sum~10 at LC8_B44
--operation mode is normal
B6L4 = B5L1 $ a[5] $ b[5];
--B7_Sum is fulladder:f6|Sum at LC3_B44
--operation mode is normal
B7_Sum = B6L1 $ a[6] $ b[6];
--B7L4 is fulladder:f6|Sum~10 at LC3_B44
--operation mode is normal
B7L4 = B6L1 $ a[6] $ b[6];
--B8_Sum is fulladder:f7|Sum at LC7_C50
--operation mode is normal
B8_Sum = B7L1 $ a[7] $ b[7];
--B8L4 is fulladder:f7|Sum~10 at LC7_C50
--operation mode is normal
B8L4 = B7L1 $ a[7] $ b[7];
--a[7] is a[7] at PIN_75
--operation mode is input
a[7] = INPUT();
--b[7] is b[7] at PIN_61
--operation mode is input
b[7] = INPUT();
--a[6] is a[6] at PIN_74
--operation mode is input
a[6] = INPUT();
--b[6] is b[6] at PIN_60
--operation mode is input
b[6] = INPUT();
--a[5] is a[5] at PIN_73
--operation mode is input
a[5] = INPUT();
--b[5] is b[5] at PIN_58
--operation mode is input
b[5] = INPUT();
--a[4] is a[4] at PIN_71
--operation mode is input
a[4] = INPUT();
--b[4] is b[4] at PIN_57
--operation mode is input
b[4] = INPUT();
--a[3] is a[3] at PIN_70
--operation mode is input
a[3] = INPUT();
--b[3] is b[3] at PIN_56
--operation mode is input
b[3] = INPUT();
--a[2] is a[2] at PIN_69
--operation mode is input
a[2] = INPUT();
--b[2] is b[2] at PIN_55
--operation mode is input
b[2] = INPUT();
--a[1] is a[1] at PIN_68
--operation mode is input
a[1] = INPUT();
--b[1] is b[1] at PIN_54
--operation mode is input
b[1] = INPUT();
--b[0] is b[0] at PIN_53
--operation mode is input
b[0] = INPUT();
--cin is cin at PIN_93
--operation mode is input
cin = INPUT();
--a[0] is a[0] at PIN_67
--operation mode is input
a[0] = INPUT();
--cout is cout at PIN_17
--operation mode is output
cout = OUTPUT(B8L1);
--sum[0] is sum[0] at PIN_7
--operation mode is output
sum[0] = OUTPUT(B1L3);
--sum[1] is sum[1] at PIN_8
--operation mode is output
sum[1] = OUTPUT(B2_Sum);
--sum[2] is sum[2] at PIN_9
--operation mode is output
sum[2] = OUTPUT(B3_Sum);
--sum[3] is sum[3] at PIN_11
--operation mode is output
sum[3] = OUTPUT(B4_Sum);
--sum[4] is sum[4] at PIN_12
--operation mode is output
sum[4] = OUTPUT(B5_Sum);
--sum[5] is sum[5] at PIN_13
--operation mode is output
sum[5] = OUTPUT(B6_Sum);
--sum[6] is sum[6] at PIN_14
--operation mode is output
sum[6] = OUTPUT(B7_Sum);
--sum[7] is sum[7] at PIN_15
--operation mode is output
sum[7] = OUTPUT(B8_Sum);
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