📄 spi_master.rpt
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Pin Type/Use - I - Input GCK - Global clock
O - Output (b) - Buried macrocell
*********************************** FB8 ***********************************
Number of signals used by logic mapping into function block: 35
Number of function block inputs used/remaining: 35/5
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 5/3
Number of PLA product terms used/remaining: 43/5
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
N_PZ_666 3 FB8_1 66 I/O (b)
spi_intrface_rcv_shift_reg/rcv_bitcnt_int<2>
3 FB8_2 67 I/O (b)
spi_intrface_rcv_shift_reg/rcv_bitcnt_int<1>
3 FB8_3 68 I/O (b)
spi_intrface_rcv_shift_reg/rcv_bitcnt_int<0>
2 FB8_4 69 I/O (b)
rcv_data<5> 4 FB8_5 (b) (b)
spi_intrface_sck_gen_sck_int_d1 2 FB8_6 (b) (b)
spi_intrface_xmit_shift_reg_data_int<7>
6 FB8_7 (b) (b)
spi_intrface_xmit_shift_reg_data_int<6>
6 FB8_8 (b) (b)
spi_intrface_xmit_shift_reg_data_int<5>
6 FB8_9 (b) (b)
spi_intrface_xmit_shift_reg_data_int<4>
6 FB8_10 (b) (b)
spi_intrface_xmit_shift_reg_data_int<3>
6 FB8_11 (b) (b)
spi_intrface_rcv_shift_reg/_n00012
1 FB8_12 70 I/O (b)
spi_intrface_xmit_shift_reg_data_int<2>
6 FB8_13 (b) (b)
rcv_data<7> 4 FB8_14 71 I/O (b)
spi_intrface_xmit_shift_reg_data_int<1>
6 FB8_15 (b) (b)
rcv_data<6> 4 FB8_16 72 I/O (b)
Signals Used by Logic in Function Block
1: N_PZ_654 13: spi_intrface_sck_gen_sck_int
25: "spi_intrface_xmit_shift_reg_data_int<7>"
2: N_PZ_662 14: spi_intrface_spi_ctrl_sm_spi_state_fft2
26: uc_intrface_cpol
3: "rcv_data<4>" 15: spi_intrface_spi_ctrl_sm_spi_state_fft3
27: uc_intrface_rcv_cpol
4: "rcv_data<5>" 16: spi_intrface_spi_ctrl_sm_spi_state_fft4
28: uc_intrface_spien
5: "rcv_data<6>" 17: spi_intrface_spi_ctrl_sm_ss_in_int
29: "uc_intrface_spitr<1>"
6: sck 18: "spi_intrface_xmit_shift_reg_data_int<0>"
30: "uc_intrface_spitr<2>"
7: sck.PIN 19: "spi_intrface_xmit_shift_reg_data_int<1>"
31: "uc_intrface_spitr<3>"
8: "spi_intrface_rcv_shift_reg/_n00012"
20: "spi_intrface_xmit_shift_reg_data_int<2>"
32: "uc_intrface_spitr<4>"
9: "spi_intrface_rcv_shift_reg/rcv_bitcnt_int<0>"
21: "spi_intrface_xmit_shift_reg_data_int<3>"
33: "uc_intrface_spitr<5>"
10: "spi_intrface_rcv_shift_reg/rcv_bitcnt_int<1>"
22: "spi_intrface_xmit_shift_reg_data_int<4>"
34: "uc_intrface_spitr<6>"
11: "spi_intrface_rcv_shift_reg/rcv_bitcnt_int<2>"
23: "spi_intrface_xmit_shift_reg_data_int<5>"
35: "uc_intrface_spitr<7>"
12: spi_intrface_sck_gen_sck_d1
24: "spi_intrface_xmit_shift_reg_data_int<6>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
N_PZ_666 X....X..XXXX.............XX............. 8 8
spi_intrface_rcv_shift_reg/rcv_bitcnt_int<2>
......XXXX.............................. 4 4
spi_intrface_rcv_shift_reg/rcv_bitcnt_int<1>
......XXX............................... 3 3
spi_intrface_rcv_shift_reg/rcv_bitcnt_int<0>
......XX................................ 2 2
rcv_data<5> X.X...X.........X..........X............ 5 5
spi_intrface_sck_gen_sck_int_d1
............X..............X............ 2 2
spi_intrface_xmit_shift_reg_data_int<7>
.X...........XXXX......XX..X......X..... 9 9
spi_intrface_xmit_shift_reg_data_int<6>
.X...........XXXX.....XX...X.....X...... 9 9
spi_intrface_xmit_shift_reg_data_int<5>
.X...........XXXX....XX....X....X....... 9 9
spi_intrface_xmit_shift_reg_data_int<4>
.X...........XXXX...XX.....X...X........ 9 9
spi_intrface_xmit_shift_reg_data_int<3>
.X...........XXXX..XX......X..X......... 9 9
spi_intrface_rcv_shift_reg/_n00012
X..........................X............ 2 2
spi_intrface_xmit_shift_reg_data_int<2>
.X...........XXXX.XX.......X.X.......... 9 9
rcv_data<7> X...X.X.........X..........X............ 5 5
spi_intrface_xmit_shift_reg_data_int<1>
.X...........XXXXXX........XX........... 9 9
rcv_data<6> X..X..X.........X..........X............ 5 5
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output (b) - Buried macrocell
*********************************** FB9 ***********************************
Number of signals used by logic mapping into function block: 12
Number of function block inputs used/remaining: 12/28
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 3/5
Number of PLA product terms used/remaining: 11/37
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
rcv_full 3 FB9_1 2 I/O O
(unused) 0 FB9_2 1 I/O
(unused) 0 FB9_3 (b)
(unused) 0 FB9_4 (b)
(unused) 0 FB9_5 143 I/O
spi_intrface_spi_ctrl_sm__n00822 1 FB9_6 (b) (b)
spi_intrface_spi_ctrl_sm_bit_cnt_reset
1 FB9_7 (b) (b)
spi_intrface_spi_ctrl_sm__n0076 3 FB9_8 (b) (b)
spi_intrface_spi_ctrl_sm_bit_cnt<2>
3 FB9_9 (b) (b)
spi_intrface_spi_ctrl_sm_bit_cnt<1>
3 FB9_10 (b) (b)
spi_intrface_spi_ctrl_sm_bit_cnt<0>
3 FB9_11 (b) (b)
spi_intrface_spi_ctrl_sm__n00832 1 FB9_12 (b) (b)
(unused) 0 FB9_13 142 I/O
(unused) 0 FB9_14 141 I/O
(unused) 0 FB9_15 140 I/O
(unused) 0 FB9_16 139 I/O
Signals Used by Logic in Function Block
1: N_PZ_662 5: "spi_intrface_spi_ctrl_sm_bit_cnt<0>"
9: spi_intrface_spi_ctrl_sm_ss_in_int
2: N_PZ_666 6: "spi_intrface_spi_ctrl_sm_bit_cnt<1>"
10: uc_intrface_rcv_full_reset
3: N_PZ_724 7: "spi_intrface_spi_ctrl_sm_bit_cnt<2>"
11: uc_intrface_spien
4: spi_intrface_spi_ctrl_sm__n00832
8: spi_intrface_spi_ctrl_sm_bit_cnt_reset
12: uc_intrface_xmit_empty_reset
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
rcv_full ...X.....XX............................. 3 3
spi_intrface_spi_ctrl_sm__n00822
X..........X............................ 2 2
spi_intrface_spi_ctrl_sm_bit_cnt_reset
..X.....X............................... 2 2
spi_intrface_spi_ctrl_sm__n0076
..X.XXXX................................ 5 5
spi_intrface_spi_ctrl_sm_bit_cnt<2>
..X.XX.X................................ 4 4
spi_intrface_spi_ctrl_sm_bit_cnt<1>
..X.X..X................................ 3 3
spi_intrface_spi_ctrl_sm_bit_cnt<0>
..X....X................................ 2 2
spi_intrface_spi_ctrl_sm__n00832
.X.......X.............................. 2 2
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output (b) - Buried macrocell
*********************************** FB10 ***********************************
Number of signals used by logic mapping into function block: 3
Number of function block inputs used/remaining: 3/37
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 2/6
Number of PLA product terms used/remaining: 3/45
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
(unused) 0 FB10_1 4TDI/I/O
(unused) 0 FB10_2 (b)
xmit_empty 4 FB10_3 5 I/O O
(unused) 0 FB10_4 6 I/O
(unused) 0 FB10_5 7 I/O
(unused) 0 FB10_6 (b)
(unused) 0 FB10_7 (b)
(unused) 0 FB10_8 (b)
(unused) 0 FB10_9 (b)
(unused) 0 FB10_10 (b)
(unused) 0 FB10_11 (b)
(unused) 0 FB10_12 8 I/O
(unused) 0 FB10_13 (b)
(unused) 0 FB10_14 9 I/O
(unused) 0 FB10_15 10 I/O
(unused) 0 FB10_16 11 I/O
Signals Used by Logic in Function Block
1: spi_intrface_spi_ctrl_sm__n00822
2: uc_intrface_spien 3: uc_intrface_xmit_empty_reset
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
xmit_empty XXX..................................... 3 3
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output (b) - Buried macrocell
*********************************** FB11 ***********************************
Number of signals used by logic mapping into function block: 0
Number of function block inputs used/remaining: 0/40
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 0/8
Number of PLA product terms used/remaining: 0/48
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
(unused) 0 FB11_1 (b)
(unused) 0 FB11_2 (b)
(unused) 0 FB11_3 138 I/O
(unused) 0 FB11_4 (b)
(unused) 0 FB11_5 137 I/O
(unused) 0 FB11_6 (b)
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