spi_master.rpt

SPI的VHDL程序

Signals Used by Logic in Function Block
  1: N_PZ_654          10: int_n             18: "uc_intrface_spissr<1>" 
  2: "addr_data<0>".PIN 
                       11: rcv_full          19: "uc_intrface_spissr<2>" 
  3: "addr_data<1>".PIN 
                       12: reset             20: "uc_intrface_spissr<3>" 
  4: "addr_data<2>".PIN 
                       13: spi_intrface_spi_ctrl_sm_ss_in_int 
                                             21: "uc_intrface_spissr<4>" 
  5: "addr_data<3>".PIN 
                       14: uc_intrface_inten 22: "uc_intrface_spissr<5>" 
  6: "addr_data<4>".PIN 
                       15: uc_intrface_rcv_full_reset 
                                             23: uc_intrface_start 
  7: "addr_data<5>".PIN 
                       16: uc_intrface_spierr 
                                             24: uc_intrface_xmit_empty_reset 
  8: "addr_data<6>".PIN 
                       17: uc_intrface_spierr_reset 
                                             25: xmit_empty 
  9: "addr_data<7>".PIN 
                      

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
uc_intrface_bb    X..........X............................ 2       2
uc_intrface_address_low<7> 
                  ........X..X............................ 2       2
int_n             .........XXX.XXXX.....XXX............... 10      10
ss_n<1>           X................X...................... 2       2
ss_n<2>           X.................X..................... 2       2
uc_intrface_address_low<6> 
                  .......X...X............................ 2       2
uc_intrface_address_low<5> 
                  ......X....X............................ 2       2
uc_intrface_address_low<4> 
                  .....X.....X............................ 2       2
uc_intrface_address_low<3> 
                  ....X......X............................ 2       2
uc_intrface_address_low<2> 
                  ...X.......X............................ 2       2
uc_intrface_address_low<1> 
                  ..X........X............................ 2       2
ss_n<3>           X..................X.................... 2       2
uc_intrface_address_low<0> 
                  .X.........X............................ 2       2
ss_n<4>           X...................X................... 2       2
ss_n<5>           X....................X.................. 2       2
uc_intrface_spierr 
                  ...........XX...X....................... 3       3
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB6 ***********************************
Number of signals used by logic mapping into function block:  32
Number of function block inputs used/remaining:               32/8
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  4/4
Number of PLA product terms used/remaining:                   34/14
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
rcv_data<1>                         5    FB6_1           (b)   (b)
mosi                                3    FB6_2      55   I/O     O
sck                                 5    FB6_3      56   I/O   I/O
uc_intrface_spirr<0>                5    FB6_4           (b)   (b)
ss_n<6>                             3    FB6_5      60   I/O     O
uc_intrface_spirr<7>                3    FB6_6           (b)   (b)
uc_intrface_spirr<6>                3    FB6_7           (b)   (b)
uc_intrface_spirr<5>                3    FB6_8           (b)   (b)
uc_intrface_spirr<4>                3    FB6_9           (b)   (b)
uc_intrface_spirr<3>                3    FB6_10          (b)   (b)
uc_intrface_spirr<2>                3    FB6_11          (b)   (b)
ss_n<7>                             3    FB6_12     61   I/O     O
rcv_data<4>                         4    FB6_13     62   I/O   (b)
rcv_data<3>                         4    FB6_14     63   I/O   (b)
uc_intrface_spirr<1>                3    FB6_15          (b)   (b)
rcv_data<2>                         4    FB6_16     65   I/O   (b)

Signals Used by Logic in Function Block
  1: N_PZ_654          12: "spi_intrface_rcv_shift_reg/miso_neg" 
                                             23: "uc_intrface_spirr<0>" 
  2: N_PZ_666          13: "spi_intrface_rcv_shift_reg/miso_pos" 
                                             24: "uc_intrface_spirr<1>" 
  3: "rcv_data<1>"     14: spi_intrface_sck_1 
                                             25: "uc_intrface_spirr<2>" 
  4: "rcv_data<2>"     15: spi_intrface_sck_gen_sck_0 
                                             26: "uc_intrface_spirr<3>" 
  5: "rcv_data<3>"     16: spi_intrface_sck_gen_sck_d1 
                                             27: "uc_intrface_spirr<4>" 
  6: "rcv_data<4>"     17: spi_intrface_spi_ctrl_sm_ss_in_int 
                                             28: "uc_intrface_spirr<5>" 
  7: "rcv_data<5>"     18: "spi_intrface_xmit_shift_reg_data_int<7>" 
                                             29: "uc_intrface_spirr<6>" 
  8: "rcv_data<6>"     19: uc_intrface_cpha  30: "uc_intrface_spirr<7>" 
  9: "rcv_data<7>"     20: uc_intrface_cpol  31: "uc_intrface_spissr<6>" 
 10: sck.PIN           21: uc_intrface_rcv_cpol 
                                             32: "uc_intrface_spissr<7>" 
 11: "spi_intrface_rcv_shift_reg/_n00012" 
                       22: uc_intrface_spien

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
rcv_data<1>       X.X......X.XX...X...XX.................. 8       8
mosi              .................X...X.................. 2       2
sck               .............XX...XX.X.................. 5       5
uc_intrface_spirr<0> 
                  .X........XXX..X.....XX................. 7       7
ss_n<6>           X.............................X......... 2       2
uc_intrface_spirr<7> 
                  .X......X............X.......X.......... 4       4
uc_intrface_spirr<6> 
                  .X.....X.............X......X........... 4       4
uc_intrface_spirr<5> 
                  .X....X..............X.....X............ 4       4
uc_intrface_spirr<4> 
                  .X...X...............X....X............. 4       4
uc_intrface_spirr<3> 
                  .X..X................X...X.............. 4       4
uc_intrface_spirr<2> 
                  .X.X.................X..X............... 4       4
ss_n<7>           X..............................X........ 2       2
rcv_data<4>       X...X....X......X....X.................. 5       5
rcv_data<3>       X..X.....X......X....X.................. 5       5
uc_intrface_spirr<1> 
                  .XX..................X.X................ 4       4
rcv_data<2>       X.X......X......X....X.................. 5       5
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB7 ***********************************
Number of signals used by logic mapping into function block:  38
Number of function block inputs used/remaining:               38/2
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  2/6
Number of PLA product terms used/remaining:                   27/21
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB7_1      81   I/O      
spi_intrface_spi_ctrl_sm_ss_in_int
                                    2    FB7_2           (b)   (b)
spi_intrface_sck_gen_sck_d1         2    FB7_3      80   I/O   (b)
spi_intrface_xmit_shift_reg_data_int<0>
                                    5    FB7_4      79   I/O   (b)
N_PZ_662                            2    FB7_5      78   I/O   (b)
uc_intrface_prs_state_fft2          4    FB7_6           (b)   (b)
uc_intrface_prs_state_fft1          4    FB7_7           (b)   (b)
uc_intrface_address_match           2    FB7_8           (b)   (b)
uc_intrface_xmit_en                 2    FB7_9           (b)   (b)
uc_intrface_stat_en                 2    FB7_10          (b)   (b)
uc_intrface_ssel_en                 2    FB7_11          (b)   (b)
N_PZ_724                            2    FB7_12     77   I/O   (b)
uc_intrface_rcv_en                  2    FB7_13          (b)   (b)
N_PZ_654                            2    FB7_14     75   I/O   (b)
uc_intrface_dt                      3    FB7_15     74   I/O   (b)
uc_intrface_cntrl_en                2    FB7_16          (b)   (b)

Signals Used by Logic in Function Block
  1: N_PZ_662          14: spi_intrface_spi_ctrl_sm_spi_state_fft1 
                                             27: "uc_intrface_address_low<5>" 
  2: "addr<0>"         15: spi_intrface_spi_ctrl_sm_spi_state_fft2 
                                             28: "uc_intrface_address_low<6>" 
  3: "addr<1>"         16: spi_intrface_spi_ctrl_sm_spi_state_fft3 
                                             29: "uc_intrface_address_low<7>" 
  4: "addr<2>"         17: spi_intrface_spi_ctrl_sm_spi_state_fft4 
                                             30: uc_intrface_address_match 
  5: "addr<3>"         18: spi_intrface_spi_ctrl_sm_ss_in_int 
                                             31: uc_intrface_cpha 
  6: "addr<4>"         19: spi_intrface_spi_ctrl_sm_ss_in_neg 
                                             32: uc_intrface_prs_state_fft1 
  7: "addr<5>"         20: spi_intrface_spi_ctrl_sm_ss_in_pos 
                                             33: uc_intrface_prs_state_fft2 
  8: "addr<6>"         21: "spi_intrface_xmit_shift_reg_data_int<0>" 
                                             34: uc_intrface_spien 
  9: "addr<7>"         22: "uc_intrface_address_low<0>" 
                                             35: "uc_intrface_spitr<0>" 
 10: ale_n             23: "uc_intrface_address_low<1>" 
                                             36: uc_intrface_start 
 11: psen_n            24: "uc_intrface_address_low<2>" 
                                             37: wr_n 
 12: rd_n              25: "uc_intrface_address_low<3>" 
                                             38: xmit_empty 
 13: sck               26: "uc_intrface_address_low<4>" 
                                            

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
spi_intrface_spi_ctrl_sm_ss_in_int 
                  ..................XX.................... 2       2
spi_intrface_sck_gen_sck_d1 
                  ............X....................X...... 2       2
spi_intrface_xmit_shift_reg_data_int<0> 
                  X.............XXXX..X............XX..... 8       8
N_PZ_662          .............XXXX.............X....X.X.. 7       7
uc_intrface_prs_state_fft2 
                  .........X.X.................X.XX...X... 6       6
uc_intrface_prs_state_fft1 
                  .........XXX.................X.XX...X... 7       7
uc_intrface_address_match 
                  .XXXXXXXXXX............................. 10      10
uc_intrface_xmit_en 
                  .XXXXXXXXXX..........XXXXXXXX........... 18      18
uc_intrface_stat_en 
                  .XXXXXXXXXX..........XXXXXXXX........... 18      18
uc_intrface_ssel_en 
                  .XXXXXXXXXX..........XXXXXXXX........... 18      18
N_PZ_724          .............XXXX....................... 4       4
uc_intrface_rcv_en 
                  .XXXXXXXXXX..........XXXXXXXX........... 18      18
N_PZ_654          .............XXXX....................... 4       4
uc_intrface_dt    .............XXXX....................... 4       4
uc_intrface_cntrl_en 
                  .XXXXXXXXXX..........XXXXXXXX........... 18      18
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device