📄 spi_master.rpt
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Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
addr_data<0> .XX....X...X.XXXX.XX...X..XX.X.......... 14 14
ss_n<0> X.......X..........X.................... 3 3
uc_intrface_spitr<3>
.....X.......XX.........X....XX......... 6 6
uc_intrface_spissr<3>
.....X.......XX......X....X...X......... 6 6
uc_intrface_spissr<2>
....X........XX.....X.....X...X......... 6 6
uc_intrface_clkdiv<0>
.....X...X.X.XX...............X......... 6 6
uc_intrface_xmit_empty_reset
.............XX.............XXX......... 5 5
uc_intrface_spitr<0>
...X.........XX........X.....XX......... 6 6
uc_intrface_spissr<0>
...X.........XX....X......X...X......... 6 6
uc_intrface_rcv_cpol
...X.......X.XXX..............X......... 6 6
uc_intrface_rcv_full_reset
.......X.....XX.XX...................... 5 5
uc_intrface_cpha ....X......XXXX...............X......... 6 6
uc_intrface_spitr<4>
......X......XX..........X...XX......... 6 6
N_PZ_721 .......X...X.XX.X.........XX.X.......... 8 8
uc_intrface_spissr<4>
......X......XX.......X...X...X......... 6 6
uc_intrface_clkdiv<1>
......X...XX.XX...............X......... 6 6
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output (b) - Buried macrocell
*********************************** FB3 ***********************************
Number of signals used by logic mapping into function block: 38
Number of function block inputs used/remaining: 38/2
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 1/7
Number of PLA product terms used/remaining: 30/18
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
addr_data<2> 8 FB3_1 98 I/O I/O
addr_data<1> 7 FB3_2 97 I/O I/O
addr_data<3> 8 FB3_3 96 I/O I/O
addr_data<4> 8 FB3_4 94 I/O I/O
addr_data<5> 8 FB3_5 93 I/O I/O
(unused) 0 FB3_6 (b)
(unused) 0 FB3_7 (b)
(unused) 0 FB3_8 (b)
(unused) 0 FB3_9 (b)
(unused) 0 FB3_10 (b)
(unused) 0 FB3_11 (b)
(unused) 0 FB3_12 92 I/O I
(unused) 0 FB3_13 (b)
(unused) 0 FB3_14 91 I/O I
(unused) 0 FB3_15 90 I/O
(unused) 0 FB3_16 (b)
Signals Used by Logic in Function Block
1: N_PZ_721 14: uc_intrface_cpha 27: "uc_intrface_spissr<4>"
2: "addr_data<1>" 15: uc_intrface_cpol 28: "uc_intrface_spissr<5>"
3: "addr_data<2>" 16: uc_intrface_prs_state_fft1
29: "uc_intrface_spitr<1>"
4: "addr_data<3>" 17: uc_intrface_prs_state_fft2
30: "uc_intrface_spitr<2>"
5: "addr_data<4>" 18: uc_intrface_rcv_en
31: "uc_intrface_spitr<3>"
6: "addr_data<5>" 19: "uc_intrface_spirr<1>"
32: "uc_intrface_spitr<4>"
7: int_n 20: "uc_intrface_spirr<2>"
33: "uc_intrface_spitr<5>"
8: rcv_full 21: "uc_intrface_spirr<3>"
34: uc_intrface_ssel_en
9: rd_n 22: "uc_intrface_spirr<4>"
35: uc_intrface_start
10: uc_intrface_bb 23: "uc_intrface_spirr<5>"
36: uc_intrface_stat_en
11: "uc_intrface_clkdiv<0>"
24: "uc_intrface_spissr<1>"
37: uc_intrface_xmit_en
12: "uc_intrface_clkdiv<1>"
25: "uc_intrface_spissr<2>"
38: xmit_empty
13: uc_intrface_cntrl_en
26: "uc_intrface_spissr<3>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
addr_data<2> X.X....XX...XX.XXX.X....X....X...X.XX... 15 15
addr_data<1> XX......X...X.XXXXX....X....X....X.XX... 14 14
addr_data<3> X..X....X.X.X..XXX..X....X....X..X.XXX.. 15 15
addr_data<4> X...X.X.X..XX..XXX...X....X....X.X.XX... 15 15
addr_data<5> X....X..XX..X..XXX....X....X....XXXXX... 15 15
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output (b) - Buried macrocell
*********************************** FB4 ***********************************
Number of signals used by logic mapping into function block: 35
Number of function block inputs used/remaining: 35/5
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 2/6
Number of PLA product terms used/remaining: 44/4
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
addr_data<6> 8 FB4_1 114 I/O I/O
addr_data<7> 8 FB4_2 116 I/O I/O
uc_intrface_spitr<2> 3 FB4_3 117 I/O I
uc_intrface_cpol 3 FB4_4 (b) (b)
uc_intrface_start 3 FB4_5 118 I/O (b)
uc_intrface_spierr_reset 5 FB4_6 (b) (b)
uc_intrface_spitr<7> 3 FB4_7 (b) (b)
uc_intrface_spissr<7> 3 FB4_8 (b) (b)
uc_intrface_spien 3 FB4_9 (b) (b)
uc_intrface_spitr<6> 3 FB4_10 (b) (b)
uc_intrface_spissr<6> 3 FB4_11 (b) (b)
uc_intrface_spitr<5> 3 FB4_12 119 I/O (b)
uc_intrface_spissr<5> 3 FB4_13 120 I/O (b)
uc_intrface_spitr<1> 3 FB4_14 121 I/O (b)
uc_intrface_inten 3 FB4_15 (b) (b)
uc_intrface_spissr<1> 3 FB4_16 122 I/O (b)
Signals Used by Logic in Function Block
1: N_PZ_721 13: uc_intrface_inten 25: "uc_intrface_spissr<7>"
2: "addr_data<1>".PIN
14: uc_intrface_prs_state_fft1
26: "uc_intrface_spitr<1>"
3: "addr_data<2>".PIN
15: uc_intrface_prs_state_fft2
27: "uc_intrface_spitr<2>"
4: "addr_data<5>".PIN
16: uc_intrface_rcv_en
28: "uc_intrface_spitr<5>"
5: "addr_data<6>" 17: uc_intrface_spien 29: "uc_intrface_spitr<6>"
6: "addr_data<6>".PIN
18: uc_intrface_spierr
30: "uc_intrface_spitr<7>"
7: "addr_data<7>" 19: uc_intrface_spierr_reset
31: uc_intrface_ssel_en
8: "addr_data<7>".PIN
20: "uc_intrface_spirr<6>"
32: uc_intrface_start
9: rd_n 21: "uc_intrface_spirr<7>"
33: uc_intrface_stat_en
10: uc_intrface_cntrl_en
22: "uc_intrface_spissr<1>"
34: uc_intrface_xmit_en
11: uc_intrface_cpol 23: "uc_intrface_spissr<5>"
35: wr_n
12: uc_intrface_dt 24: "uc_intrface_spissr<6>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
addr_data<6> X...X...XX..XXXX.X.X...X....X.X.XX...... 15 15
addr_data<7> X.....X.XX.X.XXXX...X...X....XX.XX...... 15 15
uc_intrface_spitr<2>
..X..........XX...........X......XX..... 6 6
uc_intrface_cpol .X.......XX..XX...................X..... 6 6
uc_intrface_start
...X.....X...XX................X..X..... 6 6
uc_intrface_spierr_reset
.....X.......XX...X.............X.X..... 6 6
uc_intrface_spitr<7>
.......X.....XX..............X...XX..... 6 6
uc_intrface_spissr<7>
.......X.....XX.........X.....X...X..... 6 6
uc_intrface_spien
.......X.X...XX.X.................X..... 6 6
uc_intrface_spitr<6>
.....X.......XX.............X....XX..... 6 6
uc_intrface_spissr<6>
.....X.......XX........X......X...X..... 6 6
uc_intrface_spitr<5>
...X.........XX............X.....XX..... 6 6
uc_intrface_spissr<5>
...X.........XX.......X.......X...X..... 6 6
uc_intrface_spitr<1>
.X...........XX..........X.......XX..... 6 6
uc_intrface_inten
.....X...X..XXX...................X..... 6 6
uc_intrface_spissr<1>
.X...........XX......X........X...X..... 6 6
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output (b) - Buried macrocell
*********************************** FB5 ***********************************
Number of signals used by logic mapping into function block: 25
Number of function block inputs used/remaining: 25/15
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 3/5
Number of PLA product terms used/remaining: 22/26
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
uc_intrface_bb 2 FB5_1 89TCK/I/O (b)
uc_intrface_address_low<7> 2 FB5_2 (b) (b)
int_n 5 FB5_3 88 I/O O
ss_n<1> 3 FB5_4 87 I/O O
ss_n<2> 3 FB5_5 86 I/O O
uc_intrface_address_low<6> 2 FB5_6 (b) (b)
uc_intrface_address_low<5> 2 FB5_7 (b) (b)
uc_intrface_address_low<4> 2 FB5_8 (b) (b)
uc_intrface_address_low<3> 2 FB5_9 (b) (b)
uc_intrface_address_low<2> 2 FB5_10 (b) (b)
uc_intrface_address_low<1> 2 FB5_11 (b) (b)
ss_n<3> 3 FB5_12 84 I/O O
uc_intrface_address_low<0> 2 FB5_13 (b) (b)
ss_n<4> 3 FB5_14 83 I/O O
ss_n<5> 3 FB5_15 82 I/O O
uc_intrface_spierr 3 FB5_16 (b) (b)
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