📄 spi_master.rpt
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3 6 FB4_11 (b) (b) RESET
uc_intrface_spissr<7>
3 6 FB4_8 (b) (b) RESET
uc_intrface_spitr<0>
3 6 FB2_8 (b) (b) RESET
uc_intrface_spitr<1>
3 6 FB4_14 121 I/O (b) RESET
uc_intrface_spitr<2>
3 6 FB4_3 117 I/O I RESET
uc_intrface_spitr<3>
3 6 FB2_3 (b) (b) RESET
uc_intrface_spitr<4>
3 6 FB2_13 111 I/O I RESET
uc_intrface_spitr<5>
3 6 FB4_12 119 I/O (b) RESET
uc_intrface_spitr<6>
3 6 FB4_10 (b) (b) RESET
uc_intrface_spitr<7>
3 6 FB4_7 (b) (b) RESET
uc_intrface_ssel_en 2 18 FB7_11 (b) (b) RESET
uc_intrface_start 3 6 FB4_5 118 I/O (b) RESET
uc_intrface_stat_en 2 18 FB7_10 (b) (b) RESET
uc_intrface_xmit_empty_reset
4 5 FB2_7 (b) (b) RESET
uc_intrface_xmit_en 2 18 FB7_9 (b) (b) RESET
xmit_empty 4 3 FB10_3 FAST 5 I/O O RESET
** INPUTS **
Signal Loc Pin Pin Pin I/O
Name # Type Use Style
addr<0> FB2_5 109 I/O I
addr<1> FB2_12 110 I/O I
addr<2> FB2_13 111 I/O I
addr<3> FB2_15 112 I/O I
addr<4> FB2_16 113 I/O I
addr<5> FB1_5 102 I/O I
addr<6> FB1_12 101 I/O I
addr<7> FB1_13 100 I/O I
ale_n 128 GCK/I GCK/I
clk 127 GCK/I GCK
miso FB1_1 106 I/O I
psen_n FB1_14 99 I/O I
rd_n FB3_12 92 I/O I
reset FB3_14 91 I/O I
ss_in_n FB1_4 103 I/O I
wr_n FB4_3 117 I/O I
End of Resources Used by Successfully Mapped Logic
Legend: PU - Pull Up
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 16 30 30 43 0/0 6
FB2 16 31 31 40 1/1 7
FB3 5 38 38 30 0/5 8
FB4 16 35 35 44 0/2 8
FB5 16 25 25 22 6/0 6
FB6 16 32 32 34 3/1 7
FB7 15 38 38 27 0/0 7
FB8 16 35 35 43 0/0 7
FB9 8 12 12 11 1/0 7
FB10 1 3 3 3 1/0 7
FB11 0 0 0 0 0/0 7
FB12 0 0 0 0 0/0 6
FB13 0 0 0 0 0/0 7
FB14 0 0 0 0 0/0 7
FB15 0 0 0 0 0/0 8
FB16 0 0 0 0 0/0 7
---- ----- ----- -----
125 297 12/9 112
*********************************** FB1 ***********************************
Number of signals used by logic mapping into function block: 30
Number of function block inputs used/remaining: 30/10
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 4/4
Number of PLA product terms used/remaining: 43/5
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
spi_intrface_rcv_shift_reg/miso_neg
3 FB1_1 106 I/O I
spi_intrface_spi_ctrl_sm_spi_state_fft1
9 FB1_2 (b) (b)
spi_intrface_rcv_shift_reg/miso_pos
3 FB1_3 104TDO/I/O (b)
spi_intrface_spi_ctrl_sm_ss_in_neg
2 FB1_4 103 I/O I
spi_intrface_spi_ctrl_sm_spi_state_fft4
3 FB1_5 102 I/O I
spi_intrface_sck_gen_sck_0 11 FB1_6 (b) (b)
spi_intrface_sck_gen_sck_int 5 FB1_7 (b) (b)
spi_intrface_sck_gen__n0020 2 FB1_8 (b) (b)
spi_intrface_sck_gen_clk_cnt<3> 2 FB1_9 (b) (b)
spi_intrface_sck_gen_clk_cnt<2> 2 FB1_10 (b) (b)
spi_intrface_sck_gen_clk_cnt<1> 2 FB1_11 (b) (b)
spi_intrface_sck_1 6 FB1_12 101 I/O I
spi_intrface_spi_ctrl_sm_spi_state_fft2
4 FB1_13 100 I/O I
spi_intrface_spi_ctrl_sm_spi_state_fft3
4 FB1_14 99 I/O I
spi_intrface_spi_ctrl_sm_ss_in_pos
2 FB1_15 (b) (b)
spi_intrface_sck_gen_clk_divdr/qout<0>
1 FB1_16 (b) (b)
Signals Used by Logic in Function Block
1: N_PZ_662 11: spi_intrface_sck_gen_sck_d1
21: spi_intrface_spi_ctrl_sm_spi_state_fft4
2: N_PZ_724 12: spi_intrface_sck_gen_sck_int
22: spi_intrface_spi_ctrl_sm_ss_in_int
3: miso 13: spi_intrface_sck_gen_sck_int_d1
23: ss_in_n
4: sck 14: spi_intrface_spi_ctrl_sm__n0076
24: "uc_intrface_clkdiv<0>"
5: sck.PIN 15: "spi_intrface_spi_ctrl_sm_bit_cnt<0>"
25: "uc_intrface_clkdiv<1>"
6: spi_intrface_sck_gen__n0020
16: "spi_intrface_spi_ctrl_sm_bit_cnt<1>"
26: uc_intrface_cpha
7: "spi_intrface_sck_gen_clk_cnt<1>"
17: "spi_intrface_spi_ctrl_sm_bit_cnt<2>"
27: uc_intrface_cpol
8: "spi_intrface_sck_gen_clk_cnt<2>"
18: spi_intrface_spi_ctrl_sm_spi_state_fft1
28: uc_intrface_spien
9: "spi_intrface_sck_gen_clk_cnt<3>"
19: spi_intrface_spi_ctrl_sm_spi_state_fft2
29: uc_intrface_start
10: "spi_intrface_sck_gen_clk_divdr/qout<0>"
20: spi_intrface_spi_ctrl_sm_spi_state_fft3
30: xmit_empty
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
spi_intrface_rcv_shift_reg/miso_neg
..X.X................X.....X............ 4 4
spi_intrface_spi_ctrl_sm_spi_state_fft1
...X......XXXXXXXXXXXX...XXXXX.......... 18 18
spi_intrface_rcv_shift_reg/miso_pos
..X.X................X.....X............ 4 4
spi_intrface_spi_ctrl_sm_ss_in_neg
......................X................. 1 1
spi_intrface_spi_ctrl_sm_spi_state_fft4
...........XX....XXXXX.....X............ 8 8
spi_intrface_sck_gen_sck_0
X..X.XXXX.X......XXXX..XXXXX............ 16 16
spi_intrface_sck_gen_sck_int
.....XXXX..............XX..X............ 7 7
spi_intrface_sck_gen__n0020
......XXXX...........X.....X............ 6 6
spi_intrface_sck_gen_clk_cnt<3>
......XX.X...........X.....X............ 5 5
spi_intrface_sck_gen_clk_cnt<2>
......X..X...........X.....X............ 4 4
spi_intrface_sck_gen_clk_cnt<1>
.........X...........X.....X............ 3 3
spi_intrface_sck_1
...X......XX.....XXXX....XX............. 9 9
spi_intrface_spi_ctrl_sm_spi_state_fft2
XX.........XX....XXXXX.....X............ 10 10
spi_intrface_spi_ctrl_sm_spi_state_fft3
...........XX....XXXXX...X.XXX.......... 11 11
spi_intrface_spi_ctrl_sm_ss_in_pos
......................X................. 1 1
spi_intrface_sck_gen_clk_divdr/qout<0>
.....................X.....X............ 2 2
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output (b) - Buried macrocell
*********************************** FB2 ***********************************
Number of signals used by logic mapping into function block: 31
Number of function block inputs used/remaining: 31/9
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 2/6
Number of PLA product terms used/remaining: 40/8
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
addr_data<0> 7 FB2_1 107 I/O I/O
ss_n<0> 3 FB2_2 108 I/O O
uc_intrface_spitr<3> 3 FB2_3 (b) (b)
uc_intrface_spissr<3> 3 FB2_4 (b) (b)
uc_intrface_spissr<2> 3 FB2_5 109 I/O I
uc_intrface_clkdiv<0> 3 FB2_6 (b) (b)
uc_intrface_xmit_empty_reset 4 FB2_7 (b) (b)
uc_intrface_spitr<0> 3 FB2_8 (b) (b)
uc_intrface_spissr<0> 3 FB2_9 (b) (b)
uc_intrface_rcv_cpol 3 FB2_10 (b) (b)
uc_intrface_rcv_full_reset 4 FB2_11 (b) (b)
uc_intrface_cpha 3 FB2_12 110 I/O I
uc_intrface_spitr<4> 3 FB2_13 111 I/O I
N_PZ_721 4 FB2_14 (b) (b)
uc_intrface_spissr<4> 3 FB2_15 112 I/O I
uc_intrface_clkdiv<1> 3 FB2_16 113 I/O I
Signals Used by Logic in Function Block
1: N_PZ_654 12: uc_intrface_cntrl_en
22: "uc_intrface_spissr<3>"
2: N_PZ_721 13: uc_intrface_cpha 23: "uc_intrface_spissr<4>"
3: "addr_data<0>" 14: uc_intrface_prs_state_fft1
24: "uc_intrface_spitr<0>"
4: "addr_data<0>".PIN
15: uc_intrface_prs_state_fft2
25: "uc_intrface_spitr<3>"
5: "addr_data<2>".PIN
16: uc_intrface_rcv_cpol
26: "uc_intrface_spitr<4>"
6: "addr_data<3>".PIN
17: uc_intrface_rcv_en
27: uc_intrface_ssel_en
7: "addr_data<4>".PIN
18: uc_intrface_rcv_full_reset
28: uc_intrface_stat_en
8: rd_n 19: "uc_intrface_spirr<0>"
29: uc_intrface_xmit_empty_reset
9: spi_intrface_spi_ctrl_sm_ss_in_int
20: "uc_intrface_spissr<0>"
30: uc_intrface_xmit_en
10: "uc_intrface_clkdiv<0>"
21: "uc_intrface_spissr<2>"
31: wr_n
11: "uc_intrface_clkdiv<1>"
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