📄 spi_master.rpt
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cpldfit: version F.25 Xilinx Inc.
Fitter Report
Design Name: spi_master Date: 12-11-2002, 4:04PM
Device Used: XCR3256XL-7-TQ144
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
125/256 ( 49%) 297 /896 ( 33%) 115/256 ( 45%) 37 /116 ( 32%) 279/640 ( 44%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 14 14 | I/O : 35 77
Output : 12 12 | GCK/IO : 2 2
Bidirectional : 9 9 |
GCK : 2 2 |
---- ----
Total 37 37
MACROCELL RESOURCES:
Total Macrocells Available 256
Registered Macrocells 115
Non-registered Macrocell driving I/O 0
GLOBAL RESOURCES:
Signal 'ale_n' mapped onto global clock net GCK0.
Signal 'clk' mapped onto global clock net GCK1.
Universal Control Terms (Used/Total) : 4/4
BLOCK RESOURCES:
Total Function Block Local Control Terms (Used/Total) : 4/128
Total Foldback NANDs (Used/Total) : 0/128
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Slew Pin Pin Pin Reg Init
Name Pt Used Rate # Type Use State
N_PZ_654 2 4 FB7_14 75 I/O (b)
N_PZ_662 2 7 FB7_5 78 I/O (b)
N_PZ_666 3 8 FB8_1 66 I/O (b)
N_PZ_721 4 8 FB2_14 (b) (b)
N_PZ_724 2 4 FB7_12 77 I/O (b)
addr_data<0> 7 14 FB2_1 FAST 107 I/O I/O RESET
addr_data<1> 7 14 FB3_2 FAST 97 I/O I/O RESET
addr_data<2> 8 15 FB3_1 FAST 98 I/O I/O RESET
addr_data<3> 8 15 FB3_3 FAST 96 I/O I/O RESET
addr_data<4> 8 15 FB3_4 FAST 94 I/O I/O RESET
addr_data<5> 8 15 FB3_5 FAST 93 I/O I/O RESET
addr_data<6> 8 15 FB4_1 FAST 114 I/O I/O RESET
addr_data<7> 8 15 FB4_2 FAST 116 I/O I/O RESET
int_n 5 10 FB5_3 FAST 88 I/O O RESET
mosi 3 2 FB6_2 FAST 55 I/O O RESET
rcv_data<1> 5 8 FB6_1 (b) (b) RESET
rcv_data<2> 4 5 FB6_16 65 I/O (b) RESET
rcv_data<3> 4 5 FB6_14 63 I/O (b) RESET
rcv_data<4> 4 5 FB6_13 62 I/O (b) RESET
rcv_data<5> 4 5 FB8_5 (b) (b) RESET
rcv_data<6> 4 5 FB8_16 72 I/O (b) RESET
rcv_data<7> 4 5 FB8_14 71 I/O (b) RESET
rcv_full 3 3 FB9_1 FAST 2 I/O O RESET
sck 5 5 FB6_3 FAST 56 I/O I/O RESET
spi_intrface_rcv_shift_reg/_n00012
1 2 FB8_12 70 I/O (b)
spi_intrface_rcv_shift_reg/miso_neg
3 4 FB1_1 106 I/O I RESET
spi_intrface_rcv_shift_reg/miso_pos
3 4 FB1_3 104 TDO/I/O (b) RESET
spi_intrface_rcv_shift_reg/rcv_bitcnt_int<0>
2 2 FB8_4 69 I/O (b) RESET
spi_intrface_rcv_shift_reg/rcv_bitcnt_int<1>
3 3 FB8_3 68 I/O (b) RESET
spi_intrface_rcv_shift_reg/rcv_bitcnt_int<2>
3 4 FB8_2 67 I/O (b) RESET
spi_intrface_sck_1 6 9 FB1_12 101 I/O I
spi_intrface_sck_gen__n0020
2 6 FB1_8 (b) (b) RESET
spi_intrface_sck_gen_clk_cnt<1>
2 3 FB1_11 (b) (b) RESET
spi_intrface_sck_gen_clk_cnt<2>
2 4 FB1_10 (b) (b) RESET
spi_intrface_sck_gen_clk_cnt<3>
2 5 FB1_9 (b) (b) RESET
spi_intrface_sck_gen_clk_divdr/qout<0>
1 2 FB1_16 (b) (b) RESET
spi_intrface_sck_gen_sck_0
11 16 FB1_6 (b) (b) RESET
spi_intrface_sck_gen_sck_d1
2 2 FB7_3 80 I/O (b) RESET
spi_intrface_sck_gen_sck_int
5 7 FB1_7 (b) (b) RESET
spi_intrface_sck_gen_sck_int_d1
2 2 FB8_6 (b) (b) RESET
spi_intrface_spi_ctrl_sm__n0076
3 5 FB9_8 (b) (b) RESET
spi_intrface_spi_ctrl_sm__n00822
1 2 FB9_6 (b) (b)
spi_intrface_spi_ctrl_sm__n00832
1 2 FB9_12 (b) (b)
spi_intrface_spi_ctrl_sm_bit_cnt<0>
3 2 FB9_11 (b) (b) RESET
spi_intrface_spi_ctrl_sm_bit_cnt<1>
3 3 FB9_10 (b) (b) RESET
spi_intrface_spi_ctrl_sm_bit_cnt<2>
3 4 FB9_9 (b) (b) RESET
spi_intrface_spi_ctrl_sm_bit_cnt_reset
1 2 FB9_7 (b) (b)
spi_intrface_spi_ctrl_sm_spi_state_fft1
9 18 FB1_2 (b) (b) RESET
spi_intrface_spi_ctrl_sm_spi_state_fft2
4 10 FB1_13 100 I/O I RESET
spi_intrface_spi_ctrl_sm_spi_state_fft3
4 11 FB1_14 99 I/O I RESET
spi_intrface_spi_ctrl_sm_spi_state_fft4
3 8 FB1_5 102 I/O I RESET
spi_intrface_spi_ctrl_sm_ss_in_int
2 2 FB7_2 (b) (b) RESET
spi_intrface_spi_ctrl_sm_ss_in_neg
2 1 FB1_4 103 I/O I RESET
spi_intrface_spi_ctrl_sm_ss_in_pos
2 1 FB1_15 (b) (b) RESET
spi_intrface_xmit_shift_reg_data_int<0>
5 8 FB7_4 79 I/O (b) RESET
spi_intrface_xmit_shift_reg_data_int<1>
6 9 FB8_15 (b) (b) RESET
spi_intrface_xmit_shift_reg_data_int<2>
6 9 FB8_13 (b) (b) RESET
spi_intrface_xmit_shift_reg_data_int<3>
6 9 FB8_11 (b) (b) RESET
spi_intrface_xmit_shift_reg_data_int<4>
6 9 FB8_10 (b) (b) RESET
spi_intrface_xmit_shift_reg_data_int<5>
6 9 FB8_9 (b) (b) RESET
spi_intrface_xmit_shift_reg_data_int<6>
6 9 FB8_8 (b) (b) RESET
spi_intrface_xmit_shift_reg_data_int<7>
6 9 FB8_7 (b) (b) RESET
ss_n<0> 3 3 FB2_2 FAST 108 I/O O RESET
ss_n<1> 3 2 FB5_4 FAST 87 I/O O RESET
ss_n<2> 3 2 FB5_5 FAST 86 I/O O RESET
ss_n<3> 3 2 FB5_12 FAST 84 I/O O RESET
ss_n<4> 3 2 FB5_14 FAST 83 I/O O RESET
ss_n<5> 3 2 FB5_15 FAST 82 I/O O RESET
ss_n<6> 3 2 FB6_5 FAST 60 I/O O RESET
ss_n<7> 3 2 FB6_12 FAST 61 I/O O RESET
uc_intrface_address_low<0>
2 2 FB5_13 (b) (b) RESET
uc_intrface_address_low<1>
2 2 FB5_11 (b) (b) RESET
uc_intrface_address_low<2>
2 2 FB5_10 (b) (b) RESET
uc_intrface_address_low<3>
2 2 FB5_9 (b) (b) RESET
uc_intrface_address_low<4>
2 2 FB5_8 (b) (b) RESET
uc_intrface_address_low<5>
2 2 FB5_7 (b) (b) RESET
uc_intrface_address_low<6>
2 2 FB5_6 (b) (b) RESET
uc_intrface_address_low<7>
2 2 FB5_2 (b) (b) RESET
uc_intrface_address_match
2 10 FB7_8 (b) (b) RESET
uc_intrface_bb 2 2 FB5_1 89 TCK/I/O (b) RESET
uc_intrface_clkdiv<0>
3 6 FB2_6 (b) (b) RESET
uc_intrface_clkdiv<1>
3 6 FB2_16 113 I/O I RESET
uc_intrface_cntrl_en
2 18 FB7_16 (b) (b) RESET
uc_intrface_cpha 3 6 FB2_12 110 I/O I RESET
uc_intrface_cpol 3 6 FB4_4 (b) (b) RESET
uc_intrface_dt 3 4 FB7_15 74 I/O (b) RESET
uc_intrface_inten 3 6 FB4_15 (b) (b) RESET
uc_intrface_prs_state_fft1
4 7 FB7_7 (b) (b) RESET
uc_intrface_prs_state_fft2
4 6 FB7_6 (b) (b) RESET
uc_intrface_rcv_cpol
3 6 FB2_10 (b) (b) RESET
uc_intrface_rcv_en 2 18 FB7_13 (b) (b) RESET
uc_intrface_rcv_full_reset
4 5 FB2_11 (b) (b) RESET
uc_intrface_spien 3 6 FB4_9 (b) (b) RESET
uc_intrface_spierr 3 3 FB5_16 (b) (b) RESET
uc_intrface_spierr_reset
5 6 FB4_6 (b) (b) RESET
uc_intrface_spirr<0>
5 7 FB6_4 (b) (b) RESET
uc_intrface_spirr<1>
3 4 FB6_15 (b) (b) RESET
uc_intrface_spirr<2>
3 4 FB6_11 (b) (b) RESET
uc_intrface_spirr<3>
3 4 FB6_10 (b) (b) RESET
uc_intrface_spirr<4>
3 4 FB6_9 (b) (b) RESET
uc_intrface_spirr<5>
3 4 FB6_8 (b) (b) RESET
uc_intrface_spirr<6>
3 4 FB6_7 (b) (b) RESET
uc_intrface_spirr<7>
3 4 FB6_6 (b) (b) RESET
uc_intrface_spissr<0>
3 6 FB2_9 (b) (b) RESET
uc_intrface_spissr<1>
3 6 FB4_16 122 I/O (b) RESET
uc_intrface_spissr<2>
3 6 FB2_5 109 I/O I RESET
uc_intrface_spissr<3>
3 6 FB2_4 (b) (b) RESET
uc_intrface_spissr<4>
3 6 FB2_15 112 I/O I RESET
uc_intrface_spissr<5>
3 6 FB4_13 120 I/O (b) RESET
uc_intrface_spissr<6>
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