spi_master_timesim.vhd

SPI的VHDL程序

  signal uc_intrface_spirr_7_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_spirr_7_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_spirr_7_MC_D2 : STD_LOGIC; 
  signal rcv_data_7_MC_Q : STD_LOGIC; 
  signal rcv_data_7_MC_R_OR_PRLD : STD_LOGIC; 
  signal rcv_data_7_MC_D : STD_LOGIC; 
  signal rcv_data_7_MC_D1_PT_0 : STD_LOGIC; 
  signal rcv_data_7_MC_D1 : STD_LOGIC; 
  signal rcv_data_7_MC_D2 : STD_LOGIC; 
  signal uc_intrface_spitr_7_MC_Q : STD_LOGIC; 
  signal uc_intrface_spitr_7_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_spitr_7_MC_D : STD_LOGIC; 
  signal uc_intrface_spitr_7_MC_D1 : STD_LOGIC; 
  signal uc_intrface_spitr_7_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_spitr_7_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_spitr_7_MC_D2 : STD_LOGIC; 
  signal uc_intrface_spitr_7_MC_D_TFF : STD_LOGIC; 
  signal uc_intrface_dt_MC_Q : STD_LOGIC; 
  signal uc_intrface_dt_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_dt_MC_D : STD_LOGIC; 
  signal uc_intrface_dt_MC_D1 : STD_LOGIC; 
  signal uc_intrface_dt_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_dt_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_dt_MC_D2 : STD_LOGIC; 
  signal mosi_MC_Q : STD_LOGIC; 
  signal mosi_MC_OE : STD_LOGIC; 
  signal mosi_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal mosi_MC_R_OR_PRLD : STD_LOGIC; 
  signal mosi_MC_D : STD_LOGIC; 
  signal mosi_MC_D1_PT_0 : STD_LOGIC; 
  signal mosi_MC_D1 : STD_LOGIC; 
  signal mosi_MC_D2 : STD_LOGIC; 
  signal mosi_MC_BUFOE_OUT : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_7_MC_Q : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_7_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_7_MC_D : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_7_MC_D1 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_7_MC_D2_PT_0 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_7_MC_D2_PT_1 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_7_MC_D2_PT_2 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_7_MC_D2_PT_3 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_7_MC_D2 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_7_MC_D_TFF : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_6_MC_Q : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_6_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_6_MC_D : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_6_MC_D1 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_6_MC_D2_PT_0 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_6_MC_D2_PT_1 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_6_MC_D2_PT_2 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_6_MC_D2_PT_3 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_6_MC_D2 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_6_MC_D_TFF : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_5_MC_Q : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_5_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_5_MC_D : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_5_MC_D1 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_5_MC_D2_PT_0 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_5_MC_D2_PT_1 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_5_MC_D2_PT_2 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_5_MC_D2_PT_3 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_5_MC_D2 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_5_MC_D_TFF : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_4_MC_Q : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_4_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_4_MC_D : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_4_MC_D1 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_4_MC_D2_PT_0 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_4_MC_D2_PT_1 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_4_MC_D2_PT_2 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_4_MC_D2_PT_3 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_4_MC_D2 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_4_MC_D_TFF : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_3_MC_Q : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_3_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_3_MC_D : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_3_MC_D1 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_3_MC_D2_PT_0 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_3_MC_D2_PT_1 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_3_MC_D2_PT_2 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_3_MC_D2_PT_3 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_3_MC_D2 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_3_MC_D_TFF : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_2_MC_Q : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_2_MC_D : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_2_MC_D1 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_2_MC_D2_PT_0 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_2_MC_D2_PT_1 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_2_MC_D2_PT_2 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_2_MC_D2_PT_3 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_2_MC_D2 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_2_MC_D_TFF : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_1_MC_Q : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_1_MC_D : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_1_MC_D1 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_1_MC_D2_PT_0 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_1_MC_D2_PT_1 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_1_MC_D2_PT_2 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_1_MC_D2_PT_3 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_1_MC_D2 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_1_MC_D_TFF : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_0_MC_Q : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_0_MC_D : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_0_MC_D1 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_0_MC_D2_PT_0 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_0_MC_D2_PT_1 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_0_MC_D2_PT_2 : STD_LOGIC; 
  signal spi_intrface_xmit_shift_reg_data_int_0_MC_D2 : STD_LOGIC; 
  signal ss_n_0_MC_Q : STD_LOGIC; 
  signal ss_n_0_MC_OE : STD_LOGIC; 
  signal ss_n_0_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal ss_n_0_MC_D : STD_LOGIC; 
  signal ss_n_0_MC_D1_PT_0 : STD_LOGIC; 
  signal ss_n_0_MC_D1 : STD_LOGIC; 
  signal ss_n_0_MC_D2 : STD_LOGIC; 
  signal ss_n_0_MC_BUFOE_OUT : STD_LOGIC; 
  signal ss_n_1_MC_Q : STD_LOGIC; 
  signal ss_n_1_MC_OE : STD_LOGIC; 
  signal ss_n_1_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal ss_n_1_MC_D : STD_LOGIC; 
  signal ss_n_1_MC_D1_PT_0 : STD_LOGIC; 
  signal ss_n_1_MC_D1 : STD_LOGIC; 
  signal ss_n_1_MC_D2 : STD_LOGIC; 
  signal ss_n_1_MC_BUFOE_OUT : STD_LOGIC; 
  signal ss_n_2_MC_Q : STD_LOGIC; 
  signal ss_n_2_MC_OE : STD_LOGIC; 
  signal ss_n_2_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal ss_n_2_MC_D : STD_LOGIC; 
  signal ss_n_2_MC_D1_PT_0 : STD_LOGIC; 
  signal ss_n_2_MC_D1 : STD_LOGIC; 
  signal ss_n_2_MC_D2 : STD_LOGIC; 
  signal ss_n_2_MC_BUFOE_OUT : STD_LOGIC; 
  signal ss_n_3_MC_Q : STD_LOGIC; 
  signal ss_n_3_MC_OE : STD_LOGIC; 
  signal ss_n_3_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal ss_n_3_MC_D : STD_LOGIC; 
  signal ss_n_3_MC_D1_PT_0 : STD_LOGIC; 
  signal ss_n_3_MC_D1 : STD_LOGIC; 
  signal ss_n_3_MC_D2 : STD_LOGIC; 
  signal ss_n_3_MC_BUFOE_OUT : STD_LOGIC; 
  signal ss_n_4_MC_Q : STD_LOGIC; 
  signal ss_n_4_MC_OE : STD_LOGIC; 
  signal ss_n_4_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal ss_n_4_MC_D : STD_LOGIC; 
  signal ss_n_4_MC_D1_PT_0 : STD_LOGIC; 
  signal ss_n_4_MC_D1 : STD_LOGIC; 
  signal ss_n_4_MC_D2 : STD_LOGIC; 
  signal ss_n_4_MC_BUFOE_OUT : STD_LOGIC; 
  signal ss_n_5_MC_Q : STD_LOGIC; 
  signal ss_n_5_MC_OE : STD_LOGIC; 
  signal ss_n_5_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal ss_n_5_MC_D : STD_LOGIC; 
  signal ss_n_5_MC_D1_PT_0 : STD_LOGIC; 
  signal ss_n_5_MC_D1 : STD_LOGIC; 
  signal ss_n_5_MC_D2 : STD_LOGIC; 
  signal ss_n_5_MC_BUFOE_OUT : STD_LOGIC; 
  signal ss_n_6_MC_Q : STD_LOGIC; 
  signal ss_n_6_MC_OE : STD_LOGIC; 
  signal ss_n_6_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal ss_n_6_MC_D : STD_LOGIC; 
  signal ss_n_6_MC_D1_PT_0 : STD_LOGIC; 
  signal ss_n_6_MC_D1 : STD_LOGIC; 
  signal ss_n_6_MC_D2 : STD_LOGIC; 
  signal ss_n_6_MC_BUFOE_OUT : STD_LOGIC; 
  signal ss_n_7_MC_Q : STD_LOGIC; 
  signal ss_n_7_MC_OE : STD_LOGIC; 
  signal ss_n_7_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal ss_n_7_MC_D : STD_LOGIC; 
  signal ss_n_7_MC_D1_PT_0 : STD_LOGIC; 
  signal ss_n_7_MC_D1 : STD_LOGIC; 
  signal ss_n_7_MC_D2 : STD_LOGIC; 
  signal ss_n_7_MC_BUFOE_OUT : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal PRLD : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR5_ctinst_0_OUT : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR5_ctinst_4_OUT : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR5_ctinst_7_OUT : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR4_ctinst_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR4_ctinst_7_OUT : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_prs_state_fft1_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_prs_state_fft1_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_prs_state_fft1_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_prs_state_fft1_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_prs_state_fft1_MC_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_prs_state_fft2_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_prs_state_fft2_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_prs_state_fft2_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_prs_state_fft2_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_prs_state_fft2_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_address_match_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_address_match_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_address_match_MC_D1_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_address_match_MC_D1_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_address_match_MC_D1_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_address_match_MC_D1_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_address_match_MC_D1_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_address_match_MC_D1_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_address_match_MC_D1_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_spien_MC_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_spien_MC_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_spien_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_spien_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_cntrl_en_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_cntrl_en_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_cntrl_en_MC_D1_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_cntrl_en_MC_D1_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_cntrl_en_MC_D1_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_cntrl_en_MC_D1_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_cntrl_en_MC_D1_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_cntrl_en_MC_D1_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_cntrl_en_MC_D1_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_cntrl_en_MC_D1_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_cntrl_en_MC_D1_PT_0_IN11 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_cntrl_en_MC_D1_PT_0_IN13 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_cntrl_en_MC_D1_PT_0_IN14 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_cntrl_en_MC_D1_PT_0_IN15 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_cntrl_en_MC_D1_PT_0_IN16 : STD_LOGIC; 
  signal NlwInverterSignal_spi_intrface_spi_ctrl_sm_ss_in_int_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_spi_intrface_spi_ctrl_sm_ss_in_int_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_spi_intrface_spi_ctrl_sm_ss_in_int_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_spierr_reset_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_spierr_reset_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_spierr_reset_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_spierr_reset_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_spierr_reset_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_spierr_reset_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_spierr_reset_MC_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_spierr_reset_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_stat_en_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_stat_en_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_stat_en_MC_D1_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_stat_en_MC_D1_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_stat_en_MC_D1_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_stat_en_MC_D1_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_stat_en_MC_D1_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_stat_en_MC_D1_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_stat_en_MC_D1_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_stat_en_MC_D1_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_stat_en_MC_D1_PT_0_IN11 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_stat_en_MC_D1_PT_0_IN12 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_stat_en_MC_D1_PT_0_IN13 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_stat_en_MC_D1_PT_0_IN14 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_stat_en_MC_D1_PT_0_IN15 : STD_LOGIC; 
  signal NlwInverterSignal_uc_intrface_stat_en_MC_D1_PT_0_IN16 : STD_LOGIC;