spi_master_timesim.vhd

SPI的VHDL程序

  signal uc_intrface_spitr_2_MC_D : STD_LOGIC; 
  signal uc_intrface_spitr_2_MC_D1 : STD_LOGIC; 
  signal uc_intrface_spitr_2_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_spitr_2_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_spitr_2_MC_D2 : STD_LOGIC; 
  signal uc_intrface_spitr_2_MC_D_TFF : STD_LOGIC; 
  signal rcv_full_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal rcv_full_MC_Q : STD_LOGIC; 
  signal rcv_full_MC_R_OR_PRLD : STD_LOGIC; 
  signal rcv_full_MC_D : STD_LOGIC; 
  signal rcv_full_MC_D1_PT_0 : STD_LOGIC; 
  signal rcv_full_MC_D1 : STD_LOGIC; 
  signal rcv_full_MC_D2 : STD_LOGIC; 
  signal addr_data_3_MC_Q : STD_LOGIC; 
  signal addr_data_3_MC_OE : STD_LOGIC; 
  signal addr_data_3_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal addr_data_3_MC_R_OR_PRLD : STD_LOGIC; 
  signal addr_data_3_MC_D : STD_LOGIC; 
  signal addr_data_3_MC_D1 : STD_LOGIC; 
  signal addr_data_3_MC_UIM : STD_LOGIC; 
  signal addr_data_3_MC_D2_PT_0 : STD_LOGIC; 
  signal addr_data_3_MC_D2_PT_1 : STD_LOGIC; 
  signal addr_data_3_MC_D2_PT_2 : STD_LOGIC; 
  signal addr_data_3_MC_D2_PT_3 : STD_LOGIC; 
  signal addr_data_3_MC_D2_PT_4 : STD_LOGIC; 
  signal addr_data_3_MC_D2_PT_5 : STD_LOGIC; 
  signal addr_data_3_MC_D2 : STD_LOGIC; 
  signal addr_data_3_MC_BUFOE_OUT : STD_LOGIC; 
  signal uc_intrface_spissr_3_MC_Q : STD_LOGIC; 
  signal uc_intrface_spissr_3_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_spissr_3_MC_D : STD_LOGIC; 
  signal uc_intrface_spissr_3_MC_D1 : STD_LOGIC; 
  signal uc_intrface_spissr_3_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_spissr_3_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_spissr_3_MC_D2 : STD_LOGIC; 
  signal uc_intrface_spissr_3_MC_D_TFF : STD_LOGIC; 
  signal uc_intrface_spirr_3_MC_Q : STD_LOGIC; 
  signal uc_intrface_spirr_3_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_spirr_3_MC_D : STD_LOGIC; 
  signal uc_intrface_spirr_3_MC_D1 : STD_LOGIC; 
  signal uc_intrface_spirr_3_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_spirr_3_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_spirr_3_MC_D2 : STD_LOGIC; 
  signal rcv_data_3_MC_Q : STD_LOGIC; 
  signal rcv_data_3_MC_R_OR_PRLD : STD_LOGIC; 
  signal rcv_data_3_MC_D : STD_LOGIC; 
  signal rcv_data_3_MC_D1_PT_0 : STD_LOGIC; 
  signal rcv_data_3_MC_D1 : STD_LOGIC; 
  signal rcv_data_3_MC_D2 : STD_LOGIC; 
  signal uc_intrface_spitr_3_MC_Q : STD_LOGIC; 
  signal uc_intrface_spitr_3_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_spitr_3_MC_D : STD_LOGIC; 
  signal uc_intrface_spitr_3_MC_D1 : STD_LOGIC; 
  signal uc_intrface_spitr_3_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_spitr_3_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_spitr_3_MC_D2 : STD_LOGIC; 
  signal uc_intrface_spitr_3_MC_D_TFF : STD_LOGIC; 
  signal addr_data_4_MC_Q : STD_LOGIC; 
  signal addr_data_4_MC_OE : STD_LOGIC; 
  signal addr_data_4_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal addr_data_4_MC_R_OR_PRLD : STD_LOGIC; 
  signal addr_data_4_MC_D : STD_LOGIC; 
  signal addr_data_4_MC_D1 : STD_LOGIC; 
  signal addr_data_4_MC_UIM : STD_LOGIC; 
  signal addr_data_4_MC_D2_PT_0 : STD_LOGIC; 
  signal addr_data_4_MC_D2_PT_1 : STD_LOGIC; 
  signal addr_data_4_MC_D2_PT_2 : STD_LOGIC; 
  signal addr_data_4_MC_D2_PT_3 : STD_LOGIC; 
  signal int_n_MC_UIM : STD_LOGIC; 
  signal addr_data_4_MC_D2_PT_4 : STD_LOGIC; 
  signal addr_data_4_MC_D2_PT_5 : STD_LOGIC; 
  signal addr_data_4_MC_D2 : STD_LOGIC; 
  signal addr_data_4_MC_BUFOE_OUT : STD_LOGIC; 
  signal uc_intrface_spissr_4_MC_Q : STD_LOGIC; 
  signal uc_intrface_spissr_4_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_spissr_4_MC_D : STD_LOGIC; 
  signal uc_intrface_spissr_4_MC_D1 : STD_LOGIC; 
  signal uc_intrface_spissr_4_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_spissr_4_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_spissr_4_MC_D2 : STD_LOGIC; 
  signal uc_intrface_spissr_4_MC_D_TFF : STD_LOGIC; 
  signal uc_intrface_spirr_4_MC_Q : STD_LOGIC; 
  signal uc_intrface_spirr_4_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_spirr_4_MC_D : STD_LOGIC; 
  signal uc_intrface_spirr_4_MC_D1 : STD_LOGIC; 
  signal uc_intrface_spirr_4_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_spirr_4_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_spirr_4_MC_D2 : STD_LOGIC; 
  signal rcv_data_4_MC_Q : STD_LOGIC; 
  signal rcv_data_4_MC_R_OR_PRLD : STD_LOGIC; 
  signal rcv_data_4_MC_D : STD_LOGIC; 
  signal rcv_data_4_MC_D1_PT_0 : STD_LOGIC; 
  signal rcv_data_4_MC_D1 : STD_LOGIC; 
  signal rcv_data_4_MC_D2 : STD_LOGIC; 
  signal uc_intrface_spitr_4_MC_Q : STD_LOGIC; 
  signal uc_intrface_spitr_4_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_spitr_4_MC_D : STD_LOGIC; 
  signal uc_intrface_spitr_4_MC_D1 : STD_LOGIC; 
  signal uc_intrface_spitr_4_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_spitr_4_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_spitr_4_MC_D2 : STD_LOGIC; 
  signal uc_intrface_spitr_4_MC_D_TFF : STD_LOGIC; 
  signal int_n_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal int_n_MC_Q : STD_LOGIC; 
  signal int_n_MC_D : STD_LOGIC; 
  signal int_n_MC_D1 : STD_LOGIC; 
  signal int_n_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_inten : STD_LOGIC; 
  signal uc_intrface_spierr : STD_LOGIC; 
  signal int_n_MC_D2_PT_1 : STD_LOGIC; 
  signal int_n_MC_D2_PT_2 : STD_LOGIC; 
  signal int_n_MC_D2_PT_3 : STD_LOGIC; 
  signal int_n_MC_D2 : STD_LOGIC; 
  signal uc_intrface_inten_MC_Q : STD_LOGIC; 
  signal uc_intrface_inten_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_inten_MC_D : STD_LOGIC; 
  signal uc_intrface_inten_MC_D1 : STD_LOGIC; 
  signal uc_intrface_inten_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_inten_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_inten_MC_D2 : STD_LOGIC; 
  signal uc_intrface_inten_MC_D_TFF : STD_LOGIC; 
  signal uc_intrface_spierr_MC_Q : STD_LOGIC; 
  signal uc_intrface_spierr_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_spierr_MC_D : STD_LOGIC; 
  signal uc_intrface_spierr_MC_D1_PT_0 : STD_LOGIC; 
  signal uc_intrface_spierr_MC_D1 : STD_LOGIC; 
  signal uc_intrface_spierr_MC_D2 : STD_LOGIC; 
  signal addr_data_5_MC_Q : STD_LOGIC; 
  signal addr_data_5_MC_OE : STD_LOGIC; 
  signal addr_data_5_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal addr_data_5_MC_R_OR_PRLD : STD_LOGIC; 
  signal addr_data_5_MC_D : STD_LOGIC; 
  signal addr_data_5_MC_D1 : STD_LOGIC; 
  signal addr_data_5_MC_UIM : STD_LOGIC; 
  signal addr_data_5_MC_D2_PT_0 : STD_LOGIC; 
  signal addr_data_5_MC_D2_PT_1 : STD_LOGIC; 
  signal addr_data_5_MC_D2_PT_2 : STD_LOGIC; 
  signal addr_data_5_MC_D2_PT_3 : STD_LOGIC; 
  signal uc_intrface_bb : STD_LOGIC; 
  signal addr_data_5_MC_D2_PT_4 : STD_LOGIC; 
  signal addr_data_5_MC_D2_PT_5 : STD_LOGIC; 
  signal addr_data_5_MC_D2 : STD_LOGIC; 
  signal addr_data_5_MC_BUFOE_OUT : STD_LOGIC; 
  signal uc_intrface_spissr_5_MC_Q : STD_LOGIC; 
  signal uc_intrface_spissr_5_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_spissr_5_MC_D : STD_LOGIC; 
  signal uc_intrface_spissr_5_MC_D1 : STD_LOGIC; 
  signal uc_intrface_spissr_5_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_spissr_5_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_spissr_5_MC_D2 : STD_LOGIC; 
  signal uc_intrface_spissr_5_MC_D_TFF : STD_LOGIC; 
  signal uc_intrface_spirr_5_MC_Q : STD_LOGIC; 
  signal uc_intrface_spirr_5_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_spirr_5_MC_D : STD_LOGIC; 
  signal uc_intrface_spirr_5_MC_D1 : STD_LOGIC; 
  signal uc_intrface_spirr_5_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_spirr_5_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_spirr_5_MC_D2 : STD_LOGIC; 
  signal rcv_data_5_MC_Q : STD_LOGIC; 
  signal rcv_data_5_MC_R_OR_PRLD : STD_LOGIC; 
  signal rcv_data_5_MC_D : STD_LOGIC; 
  signal rcv_data_5_MC_D1_PT_0 : STD_LOGIC; 
  signal rcv_data_5_MC_D1 : STD_LOGIC; 
  signal rcv_data_5_MC_D2 : STD_LOGIC; 
  signal uc_intrface_spitr_5_MC_Q : STD_LOGIC; 
  signal uc_intrface_spitr_5_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_spitr_5_MC_D : STD_LOGIC; 
  signal uc_intrface_spitr_5_MC_D1 : STD_LOGIC; 
  signal uc_intrface_spitr_5_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_spitr_5_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_spitr_5_MC_D2 : STD_LOGIC; 
  signal uc_intrface_spitr_5_MC_D_TFF : STD_LOGIC; 
  signal uc_intrface_bb_MC_Q : STD_LOGIC; 
  signal uc_intrface_bb_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_bb_MC_D : STD_LOGIC; 
  signal uc_intrface_bb_MC_D1_PT_0 : STD_LOGIC; 
  signal uc_intrface_bb_MC_D1 : STD_LOGIC; 
  signal uc_intrface_bb_MC_D2 : STD_LOGIC; 
  signal addr_data_6_MC_Q : STD_LOGIC; 
  signal addr_data_6_MC_OE : STD_LOGIC; 
  signal addr_data_6_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal addr_data_6_MC_R_OR_PRLD : STD_LOGIC; 
  signal addr_data_6_MC_D : STD_LOGIC; 
  signal addr_data_6_MC_D1 : STD_LOGIC; 
  signal addr_data_6_MC_UIM : STD_LOGIC; 
  signal addr_data_6_MC_D2_PT_0 : STD_LOGIC; 
  signal addr_data_6_MC_D2_PT_1 : STD_LOGIC; 
  signal addr_data_6_MC_D2_PT_2 : STD_LOGIC; 
  signal addr_data_6_MC_D2_PT_3 : STD_LOGIC; 
  signal addr_data_6_MC_D2_PT_4 : STD_LOGIC; 
  signal addr_data_6_MC_D2_PT_5 : STD_LOGIC; 
  signal addr_data_6_MC_D2 : STD_LOGIC; 
  signal addr_data_6_MC_BUFOE_OUT : STD_LOGIC; 
  signal uc_intrface_spissr_6_MC_Q : STD_LOGIC; 
  signal uc_intrface_spissr_6_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_spissr_6_MC_D : STD_LOGIC; 
  signal uc_intrface_spissr_6_MC_D1 : STD_LOGIC; 
  signal uc_intrface_spissr_6_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_spissr_6_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_spissr_6_MC_D2 : STD_LOGIC; 
  signal uc_intrface_spissr_6_MC_D_TFF : STD_LOGIC; 
  signal uc_intrface_spirr_6_MC_Q : STD_LOGIC; 
  signal uc_intrface_spirr_6_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_spirr_6_MC_D : STD_LOGIC; 
  signal uc_intrface_spirr_6_MC_D1 : STD_LOGIC; 
  signal uc_intrface_spirr_6_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_spirr_6_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_spirr_6_MC_D2 : STD_LOGIC; 
  signal rcv_data_6_MC_Q : STD_LOGIC; 
  signal rcv_data_6_MC_R_OR_PRLD : STD_LOGIC; 
  signal rcv_data_6_MC_D : STD_LOGIC; 
  signal rcv_data_6_MC_D1_PT_0 : STD_LOGIC; 
  signal rcv_data_6_MC_D1 : STD_LOGIC; 
  signal rcv_data_6_MC_D2 : STD_LOGIC; 
  signal uc_intrface_spitr_6_MC_Q : STD_LOGIC; 
  signal uc_intrface_spitr_6_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_spitr_6_MC_D : STD_LOGIC; 
  signal uc_intrface_spitr_6_MC_D1 : STD_LOGIC; 
  signal uc_intrface_spitr_6_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_spitr_6_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_spitr_6_MC_D2 : STD_LOGIC; 
  signal uc_intrface_spitr_6_MC_D_TFF : STD_LOGIC; 
  signal addr_data_7_MC_Q : STD_LOGIC; 
  signal addr_data_7_MC_OE : STD_LOGIC; 
  signal addr_data_7_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal addr_data_7_MC_R_OR_PRLD : STD_LOGIC; 
  signal addr_data_7_MC_D : STD_LOGIC; 
  signal addr_data_7_MC_D1 : STD_LOGIC; 
  signal addr_data_7_MC_UIM : STD_LOGIC; 
  signal addr_data_7_MC_D2_PT_0 : STD_LOGIC; 
  signal addr_data_7_MC_D2_PT_1 : STD_LOGIC; 
  signal addr_data_7_MC_D2_PT_2 : STD_LOGIC; 
  signal addr_data_7_MC_D2_PT_3 : STD_LOGIC; 
  signal uc_intrface_dt : STD_LOGIC; 
  signal addr_data_7_MC_D2_PT_4 : STD_LOGIC; 
  signal addr_data_7_MC_D2_PT_5 : STD_LOGIC; 
  signal addr_data_7_MC_D2 : STD_LOGIC; 
  signal addr_data_7_MC_BUFOE_OUT : STD_LOGIC; 
  signal uc_intrface_spissr_7_MC_Q : STD_LOGIC; 
  signal uc_intrface_spissr_7_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_spissr_7_MC_D : STD_LOGIC; 
  signal uc_intrface_spissr_7_MC_D1 : STD_LOGIC; 
  signal uc_intrface_spissr_7_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_spissr_7_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_spissr_7_MC_D2 : STD_LOGIC; 
  signal uc_intrface_spissr_7_MC_D_TFF : STD_LOGIC; 
  signal uc_intrface_spirr_7_MC_Q : STD_LOGIC; 
  signal uc_intrface_spirr_7_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_spirr_7_MC_D : STD_LOGIC; 
  signal uc_intrface_spirr_7_MC_D1 : STD_LOGIC;