spi_master_timesim.vhd

SPI的VHDL程序

  signal uc_intrface_xmit_empty_reset_MC_D2_PT_2 : STD_LOGIC; 
  signal uc_intrface_xmit_empty_reset_MC_D2 : STD_LOGIC; 
  signal uc_intrface_xmit_empty_reset_MC_D_TFF : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_n00822_MC_Q : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_n00822_MC_D : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_n00822_MC_D1_PT_0 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_n00822_MC_D1 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_n00822_MC_D2 : STD_LOGIC; 
  signal xmit_empty_MC_D1_PT_0 : STD_LOGIC; 
  signal xmit_empty_MC_D1 : STD_LOGIC; 
  signal xmit_empty_MC_D2 : STD_LOGIC; 
  signal uc_intrface_start_MC_Q : STD_LOGIC; 
  signal uc_intrface_start_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_start_MC_D : STD_LOGIC; 
  signal uc_intrface_start_MC_D1 : STD_LOGIC; 
  signal uc_intrface_start_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_start_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_start_MC_D2 : STD_LOGIC; 
  signal uc_intrface_start_MC_D_TFF : STD_LOGIC; 
  signal uc_intrface_cpol_MC_Q : STD_LOGIC; 
  signal uc_intrface_cpol_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_cpol_MC_D : STD_LOGIC; 
  signal uc_intrface_cpol_MC_D1 : STD_LOGIC; 
  signal uc_intrface_cpol_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_cpol_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_cpol_MC_D2 : STD_LOGIC; 
  signal uc_intrface_cpol_MC_D_TFF : STD_LOGIC; 
  signal uc_intrface_cpha_MC_Q : STD_LOGIC; 
  signal uc_intrface_cpha_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_cpha_MC_D : STD_LOGIC; 
  signal uc_intrface_cpha_MC_D1 : STD_LOGIC; 
  signal uc_intrface_cpha_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_cpha_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_cpha_MC_D2 : STD_LOGIC; 
  signal uc_intrface_cpha_MC_D_TFF : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_bit_cnt_0_MC_Q : STD_LOGIC; 
  signal FOOBAR9_ctinst_1 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_bit_cnt_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_bit_cnt_0_MC_D : STD_LOGIC; 
  signal FOOBAR9_ctinst_0 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_bit_cnt_reset : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_n00832 : STD_LOGIC; 
  signal FOOBAR9_ctinst_4 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_bit_cnt_reset_MC_Q : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_bit_cnt_reset_MC_D : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_bit_cnt_reset_MC_D1_PT_0 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_bit_cnt_reset_MC_D1 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_bit_cnt_reset_MC_D2 : STD_LOGIC; 
  signal N_PZ_724_MC_Q : STD_LOGIC; 
  signal N_PZ_724_MC_D : STD_LOGIC; 
  signal N_PZ_724_MC_D1 : STD_LOGIC; 
  signal N_PZ_724_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_724_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_724_MC_D2 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_n00832_MC_Q : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_n00832_MC_D : STD_LOGIC; 
  signal uc_intrface_rcv_full_reset : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_n00832_MC_D1_PT_0 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_n00832_MC_D1 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_n00832_MC_D2 : STD_LOGIC; 
  signal uc_intrface_rcv_full_reset_MC_Q : STD_LOGIC; 
  signal uc_intrface_rcv_full_reset_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_rcv_full_reset_MC_D : STD_LOGIC; 
  signal uc_intrface_rcv_full_reset_MC_D1 : STD_LOGIC; 
  signal uc_intrface_rcv_full_reset_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_rcv_full_reset_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_rcv_full_reset_MC_D2_PT_2 : STD_LOGIC; 
  signal uc_intrface_rcv_full_reset_MC_D2 : STD_LOGIC; 
  signal uc_intrface_rcv_full_reset_MC_D_TFF : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_bit_cnt_0_MC_D1_PT_0 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_bit_cnt_0_MC_D1 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_bit_cnt_0_MC_D2 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_bit_cnt_0_MC_D_TFF : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_bit_cnt_1_MC_Q : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_bit_cnt_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_bit_cnt_1_MC_D : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_bit_cnt_1_MC_D1_PT_0 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_bit_cnt_1_MC_D1 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_bit_cnt_1_MC_D2 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_bit_cnt_1_MC_D_TFF : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_bit_cnt_2_MC_Q : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_bit_cnt_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_bit_cnt_2_MC_D : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_bit_cnt_2_MC_D1_PT_0 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_bit_cnt_2_MC_D1 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_bit_cnt_2_MC_D2 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_bit_cnt_2_MC_D_TFF : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_n0076_MC_Q : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_n0076_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_n0076_MC_D : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_n0076_MC_D1_PT_0 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_n0076_MC_D1 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_n0076_MC_D2 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_n0076_MC_D_TFF : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft3_MC_D1 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft3_MC_D2_PT_0 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft3_MC_D2_PT_1 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft3_MC_D2_PT_2 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft3_MC_D2 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft3_MC_D_TFF : STD_LOGIC; 
  signal sck_MC_D1_PT_0 : STD_LOGIC; 
  signal sck_MC_D1 : STD_LOGIC; 
  signal sck_MC_D2_PT_0 : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_0 : STD_LOGIC; 
  signal sck_MC_D2_PT_1 : STD_LOGIC; 
  signal sck_MC_D2 : STD_LOGIC; 
  signal sck_MC_BUFOE_OUT : STD_LOGIC; 
  signal sck_MC_OE : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_0_MC_Q : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_0_MC_D : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_0_MC_D1 : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_0_MC_D2_PT_0 : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_0_MC_D2_PT_1 : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_0_MC_D2_PT_2 : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_0_MC_D2_PT_3 : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_0_MC_D2_PT_4 : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_0_MC_D2_PT_5 : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_0_MC_D2_PT_6 : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_0_MC_D2_PT_7 : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_0_MC_D2_PT_8 : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_0_MC_D2_PT_9 : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_0_MC_D2 : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_rcv_bitcnt_int_0_MC_Q : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_rcv_bitcnt_int_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_rcv_bitcnt_int_0_MC_D : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_rcv_bitcnt_int_0_MC_D1 : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_rcv_bitcnt_int_0_MC_D2 : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_rcv_bitcnt_int_0_MC_D_TFF : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_rcv_bitcnt_int_1_MC_Q : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_rcv_bitcnt_int_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_rcv_bitcnt_int_1_MC_D : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_rcv_bitcnt_int_1_MC_D1_PT_0 : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_rcv_bitcnt_int_1_MC_D1 : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_rcv_bitcnt_int_1_MC_D2 : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_rcv_bitcnt_int_1_MC_D_TFF : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_rcv_bitcnt_int_2_MC_Q : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_rcv_bitcnt_int_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_rcv_bitcnt_int_2_MC_D : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_rcv_bitcnt_int_2_MC_D1_PT_0 : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_rcv_bitcnt_int_2_MC_D1 : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_rcv_bitcnt_int_2_MC_D2 : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_rcv_bitcnt_int_2_MC_D_TFF : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_miso_pos_MC_Q : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_miso_pos_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_miso_pos_MC_D : STD_LOGIC; 
  signal miso_II_UIM : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_miso_pos_MC_D1_PT_0 : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_miso_pos_MC_D1 : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_miso_pos_MC_D2 : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_miso_neg_MC_Q : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_miso_neg_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_miso_neg_MC_D : STD_LOGIC; 
  signal FOOBAR1_ctinst_4_tsimcreated_inv_Q : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_miso_neg_MC_D1_PT_0 : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_miso_neg_MC_D1 : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_miso_neg_MC_D2 : STD_LOGIC; 
  signal uc_intrface_spitr_0_MC_Q : STD_LOGIC; 
  signal uc_intrface_spitr_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_spitr_0_MC_D : STD_LOGIC; 
  signal uc_intrface_spitr_0_MC_D1 : STD_LOGIC; 
  signal uc_intrface_spitr_0_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_spitr_0_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_spitr_0_MC_D2 : STD_LOGIC; 
  signal uc_intrface_spitr_0_MC_D_TFF : STD_LOGIC; 
  signal addr_data_1_MC_Q : STD_LOGIC; 
  signal addr_data_1_MC_OE : STD_LOGIC; 
  signal addr_data_1_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal addr_data_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal addr_data_1_MC_D : STD_LOGIC; 
  signal addr_data_1_MC_D1 : STD_LOGIC; 
  signal addr_data_1_MC_UIM : STD_LOGIC; 
  signal addr_data_1_MC_D2_PT_0 : STD_LOGIC; 
  signal addr_data_1_MC_D2_PT_1 : STD_LOGIC; 
  signal addr_data_1_MC_D2_PT_2 : STD_LOGIC; 
  signal addr_data_1_MC_D2_PT_3 : STD_LOGIC; 
  signal addr_data_1_MC_D2_PT_4 : STD_LOGIC; 
  signal addr_data_1_MC_D2 : STD_LOGIC; 
  signal addr_data_1_MC_BUFOE_OUT : STD_LOGIC; 
  signal FOOBAR3_ctinst_0 : STD_LOGIC; 
  signal uc_intrface_spissr_1_MC_Q : STD_LOGIC; 
  signal uc_intrface_spissr_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_spissr_1_MC_D : STD_LOGIC; 
  signal uc_intrface_spissr_1_MC_D1 : STD_LOGIC; 
  signal uc_intrface_spissr_1_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_spissr_1_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_spissr_1_MC_D2 : STD_LOGIC; 
  signal uc_intrface_spissr_1_MC_D_TFF : STD_LOGIC; 
  signal uc_intrface_spirr_1_MC_Q : STD_LOGIC; 
  signal uc_intrface_spirr_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_spirr_1_MC_D : STD_LOGIC; 
  signal uc_intrface_spirr_1_MC_D1 : STD_LOGIC; 
  signal uc_intrface_spirr_1_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_spirr_1_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_spirr_1_MC_D2 : STD_LOGIC; 
  signal rcv_data_1_MC_Q : STD_LOGIC; 
  signal rcv_data_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal rcv_data_1_MC_D : STD_LOGIC; 
  signal rcv_data_1_MC_D1 : STD_LOGIC; 
  signal rcv_data_1_MC_D2_PT_0 : STD_LOGIC; 
  signal rcv_data_1_MC_D2_PT_1 : STD_LOGIC; 
  signal rcv_data_1_MC_D2_PT_2 : STD_LOGIC; 
  signal rcv_data_1_MC_D2 : STD_LOGIC; 
  signal uc_intrface_spitr_1_MC_Q : STD_LOGIC; 
  signal uc_intrface_spitr_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_spitr_1_MC_D : STD_LOGIC; 
  signal uc_intrface_spitr_1_MC_D1 : STD_LOGIC; 
  signal uc_intrface_spitr_1_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_spitr_1_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_spitr_1_MC_D2 : STD_LOGIC; 
  signal uc_intrface_spitr_1_MC_D_TFF : STD_LOGIC; 
  signal addr_data_2_MC_Q : STD_LOGIC; 
  signal addr_data_2_MC_OE : STD_LOGIC; 
  signal addr_data_2_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal addr_data_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal addr_data_2_MC_D : STD_LOGIC; 
  signal addr_data_2_MC_D1 : STD_LOGIC; 
  signal addr_data_2_MC_UIM : STD_LOGIC; 
  signal addr_data_2_MC_D2_PT_0 : STD_LOGIC; 
  signal addr_data_2_MC_D2_PT_1 : STD_LOGIC; 
  signal addr_data_2_MC_D2_PT_2 : STD_LOGIC; 
  signal addr_data_2_MC_D2_PT_3 : STD_LOGIC; 
  signal rcv_full_MC_UIM : STD_LOGIC; 
  signal addr_data_2_MC_D2_PT_4 : STD_LOGIC; 
  signal addr_data_2_MC_D2_PT_5 : STD_LOGIC; 
  signal addr_data_2_MC_D2 : STD_LOGIC; 
  signal addr_data_2_MC_BUFOE_OUT : STD_LOGIC; 
  signal uc_intrface_spissr_2_MC_Q : STD_LOGIC; 
  signal uc_intrface_spissr_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_spissr_2_MC_D : STD_LOGIC; 
  signal uc_intrface_spissr_2_MC_D1 : STD_LOGIC; 
  signal uc_intrface_spissr_2_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_spissr_2_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_spissr_2_MC_D2 : STD_LOGIC; 
  signal uc_intrface_spissr_2_MC_D_TFF : STD_LOGIC; 
  signal uc_intrface_spirr_2_MC_Q : STD_LOGIC; 
  signal uc_intrface_spirr_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_spirr_2_MC_D : STD_LOGIC; 
  signal uc_intrface_spirr_2_MC_D1 : STD_LOGIC; 
  signal uc_intrface_spirr_2_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_spirr_2_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_spirr_2_MC_D2 : STD_LOGIC; 
  signal rcv_data_2_MC_Q : STD_LOGIC; 
  signal rcv_data_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal rcv_data_2_MC_D : STD_LOGIC; 
  signal rcv_data_2_MC_D1_PT_0 : STD_LOGIC; 
  signal rcv_data_2_MC_D1 : STD_LOGIC; 
  signal rcv_data_2_MC_D2 : STD_LOGIC; 
  signal uc_intrface_spitr_2_MC_Q : STD_LOGIC; 
  signal uc_intrface_spitr_2_MC_R_OR_PRLD : STD_LOGIC;