signal.hier_info

yong VerilogHDL yu yan bianxie de pinlv fa sheng qi,shi yong ISE ruan jian da kai.

|signal
clk => clk~0.IN1
rst => rst~0.IN3
codekey[0] => codekey[0]~7.IN2
codekey[1] => codekey[1]~6.IN2
codekey[2] => codekey[2]~5.IN2
codekey[3] => codekey[3]~4.IN2
codekey[4] => codekey[4]~3.IN2
codekey[5] => codekey[5]~2.IN2
codekey[6] => codekey[6]~1.IN2
codekey[7] => codekey[7]~0.IN2
dataout[0] <= key:ke.dataout
dataout[1] <= key:ke.dataout
dataout[2] <= key:ke.dataout
dataout[3] <= key:ke.dataout
dataout[4] <= key:ke.dataout
dataout[5] <= key:ke.dataout
dataout[6] <= key:ke.dataout
dataout[7] <= key:ke.dataout
en[0] <= key:ke.en
en[1] <= key:ke.en
en[2] <= key:ke.en
en[3] <= key:ke.en
en[4] <= key:ke.en
en[5] <= key:ke.en
en[6] <= key:ke.en
en[7] <= key:ke.en
q_out[0] <= signal_gene:si.q_out
q_out[1] <= signal_gene:si.q_out
q_out[2] <= signal_gene:si.q_out
q_out[3] <= signal_gene:si.q_out
q_out[4] <= signal_gene:si.q_out
q_out[5] <= signal_gene:si.q_out
q_out[6] <= signal_gene:si.q_out
q_out[7] <= signal_gene:si.q_out


|signal|oclk:oc
clk => clk_count[15].CLK
clk => clk_count[14].CLK
clk => clk_count[13].CLK
clk => clk_count[12].CLK
clk => clk_count[11].CLK
clk => clk_count[10].CLK
clk => clk_count[9].CLK
clk => clk_count[8].CLK
clk => clk_count[7].CLK
clk => clk_count[6].CLK
clk => clk_count[5].CLK
clk => clk_count[4].CLK
clk => clk_count[3].CLK
clk => clk_count[2].CLK
clk => clk_count[1].CLK
clk => clk_count[0].CLK
clk => clkout~reg0.CLK
rst => clkout~0.OUTPUTSELECT
rst => clk_count~31.OUTPUTSELECT
rst => clk_count~30.OUTPUTSELECT
rst => clk_count~29.OUTPUTSELECT
rst => clk_count~28.OUTPUTSELECT
rst => clk_count~27.OUTPUTSELECT
rst => clk_count~26.OUTPUTSELECT
rst => clk_count~25.OUTPUTSELECT
rst => clk_count~24.OUTPUTSELECT
rst => clk_count~23.OUTPUTSELECT
rst => clk_count~22.OUTPUTSELECT
rst => clk_count~21.OUTPUTSELECT
rst => clk_count~20.OUTPUTSELECT
rst => clk_count~19.OUTPUTSELECT
rst => clk_count~18.OUTPUTSELECT
rst => clk_count~17.OUTPUTSELECT
rst => clk_count~16.OUTPUTSELECT
clkout <= clkout~reg0.DB_MAX_OUTPUT_PORT_TYPE


|signal|signal_gene:si
clkin => clkin~0.IN1
rst => address[8].ACLR
rst => address[7].ACLR
rst => address[6].ACLR
rst => address[5].ACLR
rst => address[4].ACLR
rst => address[3].ACLR
rst => address[2].ACLR
rst => address[1].ACLR
rst => address[0].ACLR
rst => m[0].ENA
rst => k[7].ENA
rst => k[6].ENA
rst => k[5].ENA
rst => k[4].ENA
rst => k[3].ENA
rst => k[2].ENA
rst => k[1].ENA
rst => k[0].ENA
rst => m[7].ENA
rst => m[6].ENA
rst => m[5].ENA
rst => m[4].ENA
rst => m[3].ENA
rst => m[2].ENA
rst => m[1].ENA
control[0] => Mux24.IN5
control[0] => Mux23.IN5
control[0] => Mux22.IN5
control[0] => Mux21.IN5
control[0] => Mux20.IN5
control[0] => Mux19.IN5
control[0] => Mux18.IN5
control[0] => Mux17.IN5
control[0] => Mux16.IN5
control[0] => Mux15.IN5
control[0] => Mux14.IN5
control[0] => Mux13.IN5
control[0] => Mux12.IN5
control[0] => Mux11.IN5
control[0] => Mux10.IN5
control[0] => Mux9.IN5
control[0] => Mux8.IN5
control[0] => Mux7.IN5
control[0] => Mux6.IN5
control[0] => Mux5.IN5
control[0] => Mux4.IN5
control[0] => Mux3.IN5
control[0] => Mux2.IN5
control[0] => Mux1.IN5
control[0] => Mux0.IN5
control[1] => Mux24.IN4
control[1] => Mux23.IN4
control[1] => Mux22.IN4
control[1] => Mux21.IN4
control[1] => Mux20.IN4
control[1] => Mux19.IN4
control[1] => Mux18.IN4
control[1] => Mux17.IN4
control[1] => Mux16.IN4
control[1] => Mux15.IN4
control[1] => Mux14.IN4
control[1] => Mux13.IN4
control[1] => Mux12.IN4
control[1] => Mux11.IN4
control[1] => Mux10.IN4
control[1] => Mux9.IN4
control[1] => Mux8.IN4
control[1] => Mux7.IN4
control[1] => Mux6.IN4
control[1] => Mux5.IN4
control[1] => Mux4.IN4
control[1] => Mux3.IN4
control[1] => Mux2.IN4
control[1] => Mux1.IN4
control[1] => Mux0.IN4
i[0] => Add1.IN9
i[0] => Mult0.IN5
i[0] => Div0.IN12
i[0] => Equal3.IN26
i[0] => Equal4.IN0
i[1] => Add1.IN8
i[1] => Mult0.IN4
i[1] => Div0.IN11
i[1] => Equal3.IN27
i[1] => Equal4.IN27
i[2] => Add1.IN7
i[2] => Mult0.IN3
i[2] => Div0.IN10
i[2] => Equal3.IN28
i[2] => Equal4.IN28
i[3] => Add1.IN6
i[3] => Mult0.IN2
i[3] => Div0.IN9
i[3] => Equal3.IN29
i[3] => Equal4.IN29
i[4] => Add1.IN5
i[4] => Mult0.IN1
i[4] => Div0.IN8
i[4] => Equal3.IN30
i[4] => Equal4.IN30
i[5] => Add1.IN4
i[5] => Mult0.IN0
i[5] => Div0.IN7
i[5] => Equal3.IN31
i[5] => Equal4.IN31
q_out[0] <= datarom:datarom_component.q
q_out[1] <= datarom:datarom_component.q
q_out[2] <= datarom:datarom_component.q
q_out[3] <= datarom:datarom_component.q
q_out[4] <= datarom:datarom_component.q
q_out[5] <= datarom:datarom_component.q
q_out[6] <= datarom:datarom_component.q
q_out[7] <= datarom:datarom_component.q


|signal|signal_gene:si|datarom:datarom_component
address[0] => address[0]~8.IN1
address[1] => address[1]~7.IN1
address[2] => address[2]~6.IN1
address[3] => address[3]~5.IN1
address[4] => address[4]~4.IN1
address[5] => address[5]~3.IN1
address[6] => address[6]~2.IN1
address[7] => address[7]~1.IN1
address[8] => address[8]~0.IN1
clock => clock~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a


|signal|signal_gene:si|datarom:datarom_component|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_ki31:auto_generated.address_a[0]
address_a[1] => altsyncram_ki31:auto_generated.address_a[1]
address_a[2] => altsyncram_ki31:auto_generated.address_a[2]
address_a[3] => altsyncram_ki31:auto_generated.address_a[3]
address_a[4] => altsyncram_ki31:auto_generated.address_a[4]
address_a[5] => altsyncram_ki31:auto_generated.address_a[5]
address_a[6] => altsyncram_ki31:auto_generated.address_a[6]
address_a[7] => altsyncram_ki31:auto_generated.address_a[7]
address_a[8] => altsyncram_ki31:auto_generated.address_a[8]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_ki31:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_ki31:auto_generated.q_a[0]
q_a[1] <= altsyncram_ki31:auto_generated.q_a[1]
q_a[2] <= altsyncram_ki31:auto_generated.q_a[2]
q_a[3] <= altsyncram_ki31:auto_generated.q_a[3]
q_a[4] <= altsyncram_ki31:auto_generated.q_a[4]
q_a[5] <= altsyncram_ki31:auto_generated.q_a[5]
q_a[6] <= altsyncram_ki31:auto_generated.q_a[6]
q_a[7] <= altsyncram_ki31:auto_generated.q_a[7]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|signal|signal_gene:si|datarom:datarom_component|altsyncram:altsyncram_component|altsyncram_ki31:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT


|signal|key:ke
clkin => cnt[15].CLK
clkin => cnt[14].CLK
clkin => cnt[13].CLK
clkin => cnt[12].CLK
clkin => cnt[11].CLK
clkin => cnt[10].CLK
clkin => cnt[9].CLK
clkin => cnt[8].CLK
clkin => cnt[7].CLK
clkin => cnt[6].CLK
clkin => cnt[5].CLK
clkin => cnt[4].CLK
clkin => cnt[3].CLK
clkin => cnt[2].CLK
clkin => cnt[1].CLK
clkin => cnt[0].CLK
clkin => en[7]~reg0.CLK
clkin => en[6]~reg0.CLK
clkin => en[5]~reg0.CLK
clkin => en[4]~reg0.CLK
clkin => en[3]~reg0.CLK
clkin => en[2]~reg0.CLK
clkin => en[1]~reg0.CLK
clkin => en[0]~reg0.CLK
rst => cnt[15].ACLR
rst => cnt[14].ACLR
rst => cnt[13].ACLR
rst => cnt[12].ACLR
rst => cnt[11].ACLR
rst => cnt[10].ACLR
rst => cnt[9].ACLR
rst => cnt[8].ACLR
rst => cnt[7].ACLR
rst => cnt[6].ACLR
rst => cnt[5].ACLR
rst => cnt[4].ACLR
rst => cnt[3].ACLR
rst => cnt[2].ACLR
rst => cnt[1].ACLR
rst => cnt[0].ACLR
rst => en[7]~reg0.PRESET
rst => en[6]~reg0.PRESET
rst => en[5]~reg0.PRESET
rst => en[4]~reg0.PRESET
rst => en[3]~reg0.PRESET
rst => en[2]~reg0.PRESET
rst => en[1]~reg0.PRESET
rst => en[0]~reg0.ACLR
datain[0] => Selector0.IN15
datain[1] => Selector0.IN14
datain[2] => Selector0.IN13
datain[3] => Selector0.IN12
datain[4] => Selector0.IN11
datain[5] => Selector0.IN10
datain[6] => Selector0.IN9
datain[7] => Selector0.IN8
dataout[0] <= <VCC>
dataout[1] <= WideOr7.DB_MAX_OUTPUT_PORT_TYPE
dataout[2] <= Decoder1.DB_MAX_OUTPUT_PORT_TYPE
dataout[3] <= Decoder1.DB_MAX_OUTPUT_PORT_TYPE
dataout[4] <= Decoder1.DB_MAX_OUTPUT_PORT_TYPE
dataout[5] <= <GND>
dataout[6] <= <GND>
dataout[7] <= Decoder1.DB_MAX_OUTPUT_PORT_TYPE
en[0] <= en[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
en[1] <= en[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
en[2] <= en[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
en[3] <= en[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
en[4] <= en[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
en[5] <= en[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
en[6] <= en[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
en[7] <= en[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE