signal.tan.qmsg

yong VerilogHDL yu yan bianxie de pinlv fa sheng qi,shi yong ISE ruan jian da kai.

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "oclk:oc\|clkout " "Info: Detected ripple clock \"oclk:oc\|clkout\" as buffer" {  } { { "oclk.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/oclk.v" 3 -1 0 } } { "e:/quartus7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "oclk:oc\|clkout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register signal_gene:si\|m\[1\] register signal_gene:si\|address\[0\] 139.8 MHz 7.153 ns Internal " "Info: Clock \"clk\" has Internal fmax of 139.8 MHz between source register \"signal_gene:si\|m\[1\]\" and destination register \"signal_gene:si\|address\[0\]\" (period= 7.153 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.951 ns + Longest register register " "Info: + Longest register to register delay is 6.951 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns signal_gene:si\|m\[1\] 1 REG LC_X15_Y6_N1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y6_N1; Fanout = 3; REG Node = 'signal_gene:si\|m\[1\]'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { signal_gene:si|m[1] } "NODE_NAME" } } { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 97 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.598 ns) + CELL(0.454 ns) 1.052 ns signal_gene:si\|LessThan2~644 2 COMB LC_X16_Y6_N1 1 " "Info: 2: + IC(0.598 ns) + CELL(0.454 ns) = 1.052 ns; Loc. = LC_X16_Y6_N1; Fanout = 1; COMB Node = 'signal_gene:si\|LessThan2~644'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.052 ns" { signal_gene:si|m[1] signal_gene:si|LessThan2~644 } "NODE_NAME" } } { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.140 ns) + CELL(0.088 ns) 1.280 ns signal_gene:si\|LessThan2~645 3 COMB LC_X16_Y6_N2 1 " "Info: 3: + IC(0.140 ns) + CELL(0.088 ns) = 1.280 ns; Loc. = LC_X16_Y6_N2; Fanout = 1; COMB Node = 'signal_gene:si\|LessThan2~645'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.228 ns" { signal_gene:si|LessThan2~644 signal_gene:si|LessThan2~645 } "NODE_NAME" } } { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.140 ns) + CELL(0.088 ns) 1.508 ns signal_gene:si\|LessThan2~646 4 COMB LC_X16_Y6_N3 1 " "Info: 4: + IC(0.140 ns) + CELL(0.088 ns) = 1.508 ns; Loc. = LC_X16_Y6_N3; Fanout = 1; COMB Node = 'signal_gene:si\|LessThan2~646'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.228 ns" { signal_gene:si|LessThan2~645 signal_gene:si|LessThan2~646 } "NODE_NAME" } } { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.140 ns) + CELL(0.088 ns) 1.736 ns signal_gene:si\|LessThan2~650 5 COMB LC_X16_Y6_N4 1 " "Info: 5: + IC(0.140 ns) + CELL(0.088 ns) = 1.736 ns; Loc. = LC_X16_Y6_N4; Fanout = 1; COMB Node = 'signal_gene:si\|LessThan2~650'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.228 ns" { signal_gene:si|LessThan2~646 signal_gene:si|LessThan2~650 } "NODE_NAME" } } { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.262 ns) + CELL(0.088 ns) 2.086 ns signal_gene:si\|LessThan2~647 6 COMB LC_X16_Y6_N5 1 " "Info: 6: + IC(0.262 ns) + CELL(0.088 ns) = 2.086 ns; Loc. = LC_X16_Y6_N5; Fanout = 1; COMB Node = 'signal_gene:si\|LessThan2~647'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.350 ns" { signal_gene:si|LessThan2~650 signal_gene:si|LessThan2~647 } "NODE_NAME" } } { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.326 ns) + CELL(0.088 ns) 2.500 ns signal_gene:si\|LessThan2~648 7 COMB LC_X16_Y6_N7 1 " "Info: 7: + IC(0.326 ns) + CELL(0.088 ns) = 2.500 ns; Loc. = LC_X16_Y6_N7; Fanout = 1; COMB Node = 'signal_gene:si\|LessThan2~648'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.414 ns" { signal_gene:si|LessThan2~647 signal_gene:si|LessThan2~648 } "NODE_NAME" } } { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.337 ns) + CELL(0.225 ns) 3.062 ns signal_gene:si\|LessThan2~649 8 COMB LC_X16_Y6_N0 2 " "Info: 8: + IC(0.337 ns) + CELL(0.225 ns) = 3.062 ns; Loc. = LC_X16_Y6_N0; Fanout = 2; COMB Node = 'signal_gene:si\|LessThan2~649'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.562 ns" { signal_gene:si|LessThan2~648 signal_gene:si|LessThan2~649 } "NODE_NAME" } } { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.335 ns) + CELL(0.088 ns) 3.485 ns signal_gene:si\|address\[4\]~1331 9 COMB LC_X16_Y6_N9 1 " "Info: 9: + IC(0.335 ns) + CELL(0.088 ns) = 3.485 ns; Loc. = LC_X16_Y6_N9; Fanout = 1; COMB Node = 'signal_gene:si\|address\[4\]~1331'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.423 ns" { signal_gene:si|LessThan2~649 signal_gene:si|address[4]~1331 } "NODE_NAME" } } { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 97 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.848 ns) + CELL(0.088 ns) 4.421 ns signal_gene:si\|address\[4\]~1334 10 COMB LC_X19_Y6_N9 1 " "Info: 10: + IC(0.848 ns) + CELL(0.088 ns) = 4.421 ns; Loc. = LC_X19_Y6_N9; Fanout = 1; COMB Node = 'signal_gene:si\|address\[4\]~1334'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.936 ns" { signal_gene:si|address[4]~1331 signal_gene:si|address[4]~1334 } "NODE_NAME" } } { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 97 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.889 ns) + CELL(0.340 ns) 5.650 ns signal_gene:si\|address\[4\]~1335 11 COMB LC_X17_Y6_N9 9 " "Info: 11: + IC(0.889 ns) + CELL(0.340 ns) = 5.650 ns; Loc. = LC_X17_Y6_N9; Fanout = 9; COMB Node = 'signal_gene:si\|address\[4\]~1335'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.229 ns" { signal_gene:si|address[4]~1334 signal_gene:si|address[4]~1335 } "NODE_NAME" } } { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 97 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.358 ns) + CELL(0.943 ns) 6.951 ns signal_gene:si\|address\[0\] 12 REG LC_X17_Y6_N0 8 " "Info: 12: + IC(0.358 ns) + CELL(0.943 ns) = 6.951 ns; Loc. = LC_X17_Y6_N0; Fanout = 8; REG Node = 'signal_gene:si\|address\[0\]'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.301 ns" { signal_gene:si|address[4]~1335 signal_gene:si|address[0] } "NODE_NAME" } } { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 97 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.578 ns ( 37.09 % ) " "Info: Total cell delay = 2.578 ns ( 37.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.373 ns ( 62.91 % ) " "Info: Total interconnect delay = 4.373 ns ( 62.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "6.951 ns" { signal_gene:si|m[1] signal_gene:si|LessThan2~644 signal_gene:si|LessThan2~645 signal_gene:si|LessThan2~646 signal_gene:si|LessThan2~650 signal_gene:si|LessThan2~647 signal_gene:si|LessThan2~648 signal_gene:si|LessThan2~649 signal_gene:si|address[4]~1331 signal_gene:si|address[4]~1334 signal_gene:si|address[4]~1335 signal_gene:si|address[0] } "NODE_NAME" } } { "e:/quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus7.2/quartus/bin/Technology_Viewer.qrui" "6.951 ns" { signal_gene:si|m[1] {} signal_gene:si|LessThan2~644 {} signal_gene:si|LessThan2~645 {} signal_gene:si|LessThan2~646 {} signal_gene:si|LessThan2~650 {} signal_gene:si|LessThan2~647 {} signal_gene:si|LessThan2~648 {} signal_gene:si|LessThan2~649 {} signal_gene:si|address[4]~1331 {} signal_gene:si|address[4]~1334 {} signal_gene:si|address[4]~1335 {} signal_gene:si|address[0] {} } { 0.000ns 0.598ns 0.140ns 0.140ns 0.140ns 0.262ns 0.326ns 0.337ns 0.335ns 0.848ns 0.889ns 0.358ns } { 0.000ns 0.454ns 0.088ns 0.088ns 0.088ns 0.088ns 0.088ns 0.225ns 0.088ns 0.088ns 0.340ns 0.943ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.516 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 5.516 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_16 17 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_16; Fanout = 17; CLK Node = 'clk'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "signal.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.430 ns) + CELL(0.720 ns) 2.280 ns oclk:oc\|clkout 2 REG LC_X8_Y6_N2 66 " "Info: 2: + IC(0.430 ns) + CELL(0.720 ns) = 2.280 ns; Loc. = LC_X8_Y6_N2; Fanout = 66; REG Node = 'oclk:oc\|clkout'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.150 ns" { clk oclk:oc|clkout } "NODE_NAME" } } { "oclk.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/oclk.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.689 ns) + CELL(0.547 ns) 5.516 ns signal_gene:si\|address\[0\] 3 REG LC_X17_Y6_N0 8 " "Info: 3: + IC(2.689 ns) + CELL(0.547 ns) = 5.516 ns; Loc. = LC_X17_Y6_N0; Fanout = 8; REG Node = 'signal_gene:si\|address\[0\]'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.236 ns" { oclk:oc|clkout signal_gene:si|address[0] } "NODE_NAME" } } { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 97 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.397 ns ( 43.46 % ) " "Info: Total cell delay = 2.397 ns ( 43.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.119 ns ( 56.54 % ) " "Info: Total interconnect delay = 3.119 ns ( 56.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.516 ns" { clk oclk:oc|clkout signal_gene:si|address[0] } "NODE_NAME" } } { "e:/quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus7.2/quartus/bin/Technology_Viewer.qrui" "5.516 ns" { clk {} clk~out0 {} oclk:oc|clkout {} signal_gene:si|address[0] {} } { 0.000ns 0.000ns 0.430ns 2.689ns } { 0.000ns 1.130ns 0.720ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.516 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 5.516 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_16 17 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_16; Fanout = 17; CLK Node = 'clk'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "signal.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.430 ns) + CELL(0.720 ns) 2.280 ns oclk:oc\|clkout 2 REG LC_X8_Y6_N2 66 " "Info: 2: + IC(0.430 ns) + CELL(0.720 ns) = 2.280 ns; Loc. = LC_X8_Y6_N2; Fanout = 66; REG Node = 'oclk:oc\|clkout'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.150 ns" { clk oclk:oc|clkout } "NODE_NAME" } } { "oclk.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/oclk.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.689 ns) + CELL(0.547 ns) 5.516 ns signal_gene:si\|m\[1\] 3 REG LC_X15_Y6_N1 3 " "Info: 3: + IC(2.689 ns) + CELL(0.547 ns) = 5.516 ns; Loc. = LC_X15_Y6_N1; Fanout = 3; REG Node = 'signal_gene:si\|m\[1\]'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.236 ns" { oclk:oc|clkout signal_gene:si|m[1] } "NODE_NAME" } } { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 97 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.397 ns ( 43.46 % ) " "Info: Total cell delay = 2.397 ns ( 43.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.119 ns ( 56.54 % ) " "Info: Total interconnect delay = 3.119 ns ( 56.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.516 ns" { clk oclk:oc|clkout signal_gene:si|m[1] } "NODE_NAME" } } { "e:/quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus7.2/quartus/bin/Technology_Viewer.qrui" "5.516 ns" { clk {} clk~out0 {} oclk:oc|clkout {} signal_gene:si|m[1] {} } { 0.000ns 0.000ns 0.430ns 2.689ns } { 0.000ns 1.130ns 0.720ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.516 ns" { clk oclk:oc|clkout signal_gene:si|address[0] } "NODE_NAME" } } { "e:/quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus7.2/quartus/bin/Technology_Viewer.qrui" "5.516 ns" { clk {} clk~out0 {} oclk:oc|clkout {} signal_gene:si|address[0] {} } { 0.000ns 0.000ns 0.430ns 2.689ns } { 0.000ns 1.130ns 0.720ns 0.547ns } "" } } { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.516 ns" { clk oclk:oc|clkout signal_gene:si|m[1] } "NODE_NAME" } } { "e:/quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus7.2/quartus/bin/Technology_Viewer.qrui" "5.516 ns" { clk {} clk~out0 {} oclk:oc|clkout {} signal_gene:si|m[1] {} } { 0.000ns 0.000ns 0.430ns 2.689ns } { 0.000ns 1.130ns 0.720ns 0.547ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 97 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 97 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "6.951 ns" { signal_gene:si|m[1] signal_gene:si|LessThan2~644 signal_gene:si|LessThan2~645 signal_gene:si|LessThan2~646 signal_gene:si|LessThan2~650 signal_gene:si|LessThan2~647 signal_gene:si|LessThan2~648 signal_gene:si|LessThan2~649 signal_gene:si|address[4]~1331 signal_gene:si|address[4]~1334 signal_gene:si|address[4]~1335 signal_gene:si|address[0] } "NODE_NAME" } } { "e:/quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus7.2/quartus/bin/Technology_Viewer.qrui" "6.951 ns" { signal_gene:si|m[1] {} signal_gene:si|LessThan2~644 {} signal_gene:si|LessThan2~645 {} signal_gene:si|LessThan2~646 {} signal_gene:si|LessThan2~650 {} signal_gene:si|LessThan2~647 {} signal_gene:si|LessThan2~648 {} signal_gene:si|LessThan2~649 {} signal_gene:si|address[4]~1331 {} signal_gene:si|address[4]~1334 {} signal_gene:si|address[4]~1335 {} signal_gene:si|address[0] {} } { 0.000ns 0.598ns 0.140ns 0.140ns 0.140ns 0.262ns 0.326ns 0.337ns 0.335ns 0.848ns 0.889ns 0.358ns } { 0.000ns 0.454ns 0.088ns 0.088ns 0.088ns 0.088ns 0.088ns 0.225ns 0.088ns 0.088ns 0.340ns 0.943ns } "" } } { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.516 ns" { clk oclk:oc|clkout signal_gene:si|address[0] } "NODE_NAME" } } { "e:/quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus7.2/quartus/bin/Technology_Viewer.qrui" "5.516 ns" { clk {} clk~out0 {} oclk:oc|clkout {} signal_gene:si|address[0] {} } { 0.000ns 0.000ns 0.430ns 2.689ns } { 0.000ns 1.130ns 0.720ns 0.547ns } "" } } { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.516 ns" { clk oclk:oc|clkout signal_gene:si|m[1] } "NODE_NAME" } } { "e:/quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus7.2/quartus/bin/Technology_Viewer.qrui" "5.516 ns" { clk {} clk~out0 {} oclk:oc|clkout {} signal_gene:si|m[1] {} } { 0.000ns 0.000ns 0.430ns 2.689ns } { 0.000ns 1.130ns 0.720ns 0.547ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}