signal.map.rpt

yong VerilogHDL yu yan bianxie de pinlv fa sheng qi,shi yong ISE ruan jian da kai.

Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------+
; lpm_mult Parameter Settings by Entity Instance                        ;
+---------------------------------------+-------------------------------+
; Name                                  ; Value                         ;
+---------------------------------------+-------------------------------+
; Number of entity instances            ; 1                             ;
; Entity Instance                       ; signal_gene:si|lpm_mult:Mult0 ;
;     -- LPM_WIDTHA                     ; 6                             ;
;     -- LPM_WIDTHB                     ; 8                             ;
;     -- LPM_WIDTHP                     ; 14                            ;
;     -- LPM_REPRESENTATION             ; UNSIGNED                      ;
;     -- INPUT_A_IS_CONSTANT            ; NO                            ;
;     -- INPUT_B_IS_CONSTANT            ; NO                            ;
;     -- USE_EAB                        ; OFF                           ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                          ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                            ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                            ;
+---------------------------------------+-------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Sat Jun 07 13:50:00 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Signal -c signal
Info: Found 1 design units, including 1 entities, in source file oclk.v
    Info: Found entity 1: oclk
Info: Found 1 design units, including 1 entities, in source file signal.v
    Info: Found entity 1: signal
Info: Found 1 design units, including 1 entities, in source file signal_gene.v
    Info: Found entity 1: signal_gene
Info: Elaborating entity "signal" for the top level hierarchy
Info: Elaborating entity "oclk" for hierarchy "oclk:oc"
Warning (10230): Verilog HDL assignment warning at oclk.v(12): truncated value with size 32 to match size of target (16)
Info: Elaborating entity "signal_gene" for hierarchy "signal_gene:si"
Warning (10230): Verilog HDL assignment warning at signal_gene.v(26): truncated value with size 32 to match size of target (9)
Warning (10230): Verilog HDL assignment warning at signal_gene.v(31): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at signal_gene.v(45): truncated value with size 32 to match size of target (9)
Warning (10230): Verilog HDL assignment warning at signal_gene.v(50): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at signal_gene.v(65): truncated value with size 32 to match size of target (9)
Warning (10230): Verilog HDL assignment warning at signal_gene.v(70): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at signal_gene.v(85): truncated value with size 32 to match size of target (9)
Warning (10230): Verilog HDL assignment warning at signal_gene.v(90): truncated value with size 32 to match size of target (8)
Warning: Using design file datarom.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: datarom
Info: Elaborating entity "datarom" for hierarchy "signal_gene:si|datarom:datarom_component"
Info: Found 1 design units, including 1 entities, in source file e:/quartus7.2/quartus/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "signal_gene:si|datarom:datarom_component|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "signal_gene:si|datarom:datarom_component|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_ki31.tdf
    Info: Found entity 1: altsyncram_ki31
Info: Elaborating entity "altsyncram_ki31" for hierarchy "signal_gene:si|datarom:datarom_component|altsyncram:altsyncram_component|altsyncram_ki31:auto_generated"
Warning: Using design file key.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: key
Info: Elaborating entity "key" for hierarchy "key:ke"
Warning (10230): Verilog HDL assignment warning at key.v(20): truncated value with size 32 to match size of target (16)
Info: Inferred 2 megafunctions from design logic
    Info: Inferred multiplier megafunction ("lpm_mult") from the following logic: "signal_gene:si|Mult0"
    Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "signal_gene:si|Div0"
Info: Found 1 design units, including 1 entities, in source file e:/quartus7.2/quartus/libraries/megafunctions/lpm_mult.tdf
    Info: Found entity 1: lpm_mult
Info: Elaborated megafunction instantiation "signal_gene:si|lpm_mult:Mult0"
Info: Found 1 design units, including 1 entities, in source file db/mult_mk01.tdf
    Info: Found entity 1: mult_mk01
Info: Found 1 design units, including 1 entities, in source file e:/quartus7.2/quartus/libraries/megafunctions/lpm_divide.tdf
    Info: Found entity 1: lpm_divide
Info: Elaborated megafunction instantiation "signal_gene:si|lpm_divide:Div0"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_g5m.tdf
    Info: Found entity 1: lpm_divide_g5m
Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_ckh.tdf
    Info: Found entity 1: sign_div_unsign_ckh
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_8oe.tdf
    Info: Found entity 1: alt_u_div_8oe
Info: Found 1 design units, including 1 entities, in source file db/add_sub_3dc.tdf
    Info: Found entity 1: add_sub_3dc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_4dc.tdf
    Info: Found entity 1: add_sub_4dc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_5dc.tdf
    Info: Found entity 1: add_sub_5dc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_6dc.tdf
    Info: Found entity 1: add_sub_6dc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_7dc.tdf
    Info: Found entity 1: add_sub_7dc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_8dc.tdf
    Info: Found entity 1: add_sub_8dc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_9dc.tdf
    Info: Found entity 1: add_sub_9dc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_79c.tdf
    Info: Found entity 1: add_sub_79c
Warning: Synthesized away the following node(s):
    Warning: Synthesized away the following LCELL buffer node(s):
        Warning (14320): Synthesized away node "signal_gene:si|lpm_mult:Mult0|mult_mk01:auto_generated|le3a[9]"
        Warning (14320): Synthesized away node "signal_gene:si|lpm_mult:Mult0|mult_mk01:auto_generated|le3a[8]"
        Warning (14320): Synthesized away node "signal_gene:si|lpm_mult:Mult0|mult_mk01:auto_generated|le4a[9]"
        Warning (14320): Synthesized away node "signal_gene:si|lpm_mult:Mult0|mult_mk01:auto_generated|le4a[8]"
        Warning (14320): Synthesized away node "signal_gene:si|lpm_mult:Mult0|mult_mk01:auto_generated|le4a[7]"
        Warning (14320): Synthesized away node "signal_gene:si|lpm_mult:Mult0|mult_mk01:auto_generated|le4a[6]"
        Warning (14320): Synthesized away node "signal_gene:si|lpm_mult:Mult0|mult_mk01:auto_generated|le5a[9]"
        Warning (14320): Synthesized away node "signal_gene:si|lpm_mult:Mult0|mult_mk01:auto_generated|le5a[8]"
        Warning (14320): Synthesized away node "signal_gene:si|lpm_mult:Mult0|mult_mk01:auto_generated|le5a[7]"
        Warning (14320): Synthesized away node "signal_gene:si|lpm_mult:Mult0|mult_mk01:auto_generated|le5a[6]"
        Warning (14320): Synthesized away node "signal_gene:si|lpm_mult:Mult0|mult_mk01:auto_generated|le5a[5]"
        Warning (14320): Synthesized away node "signal_gene:si|lpm_mult:Mult0|mult_mk01:auto_generated|le5a[4]"
        Warning (14320): Synthesized away node "signal_gene:si|lpm_mult:Mult0|mult_mk01:auto_generated|le6a[8]"
        Warning (14320): Synthesized away node "signal_gene:si|lpm_mult:Mult0|mult_mk01:auto_generated|le6a[7]"
        Warning (14320): Synthesized away node "signal_gene:si|lpm_mult:Mult0|mult_mk01:auto_generated|le6a[6]"
        Warning (14320): Synthesized away node "signal_gene:si|lpm_mult:Mult0|mult_mk01:auto_generated|le6a[5]"
        Warning (14320): Synthesized away node "signal_gene:si|lpm_mult:Mult0|mult_mk01:auto_generated|le6a[4]"
        Warning (14320): Synthesized away node "signal_gene:si|lpm_mult:Mult0|mult_mk01:auto_generated|le6a[3]"
Info: Ignored 41 buffer(s)
    Info: Ignored 41 SOFT buffer(s)
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "dataout[0]" stuck at VCC
    Warning (13410): Pin "dataout[1]" stuck at VCC
    Warning (13410): Pin "dataout[5]" stuck at GND
    Warning (13410): Pin "dataout[6]" stuck at GND
Info: Registers with preset signals will power-up high
Info: Implemented 258 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 24 output pins
    Info: Implemented 216 logic cells
    Info: Implemented 8 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 37 warnings
    Info: Allocated 148 megabytes of memory during processing
    Info: Processing ended: Sat Jun 07 13:50:15 2008
    Info: Elapsed time: 00:00:15