oclk.v

yong VerilogHDL yu yan bianxie de pinlv fa sheng qi,shi yong ISE ruan jian da kai.

module oclk(clk,rst,clkout);
    input clk,rst;
    output clkout;
    reg clkout;
    reg[15:0] clk_count;
    
    always @(posedge clk)
        begin 
          if(!rst) clk_count<=0;
          else if(clk_count==16'h0fa0)
               clk_count<=0;
               else clk_count<=clk_count+1;
    end
        
    always @(posedge clk)
        begin
          if(!rst) clkout<=0;
          else if(clk_count<=16'h07d0)
               clkout<=0;
               else clkout<=1;
        end       
endmodule